Intel P8700 - Core 2 Duo Processor Datasheet page 99

Package Mechanical Specifications and Pin Information
Table 19. Signal Description (Sheet 7 of 8)
Name
STPCLK#
TCK
TDI
TDO
TEST1,
TEST2,
TEST3,
TEST4,
TEST5,
TEST6
TEST7
THRMDA
THRMDC
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VSS
VCCA
VCCP
Datasheet
Type
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
Input The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
Input
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI
Input
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
Output TDO provides the serial output needed for JTAG specification
support.
Refer to the appropriate platform design guide for further TEST1,
Input TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination
requirements and implementation details.
Other Thermal Diode Anode.
Other Thermal Diode Cathode.
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
Output
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TMS (Test Mode Select) is a JTAG specification support signal used
Input
by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is
Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
Input
must be driven low during power on Reset.
Input Processor core power supply.
Input Processor core ground node.
Input VCCA provides isolated power for the internal processor core PLLs
Input Processor I/O Power Supply.
Description
.
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