Intel P8700 - Core 2 Duo Processor Datasheet page 95

Core 2 duo mobile processor, intel core 2 solo mobile processor and intel core 2 extreme mobile processor on 45-nm process, platforms based on mobile intel 4 series express chipset family
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Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 3 of 8)
Name
DEFER#
DINV[3:0]#
DPRSTP#
DPSLP#
DPWR#
DRDY#
DSTBN[3:0]#
Datasheet
Type
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
Input
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both
FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DINV[3:0]# Assignment To Data Bus
Input/
Bus Signal
Output
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state or
Input
Deep Power Down Technology (C6) state. To return to the Deep
Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by
the ICH9M.
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. To return to
Input
the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by
the ICH9M.
DPWR# is a control signal used by the chipset to reduce power on
Input/
the processor data bus input buffers. The processor drives this pin
Output
during dynamic FSB frequency switching
DRDY# (Data Ready) is asserted by the data driver on each data
Input/
transfer, indicating valid data on the data bus. In a multi-common
Output
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Data strobe used to latch in D[63:0]#.
Signals
Input/
D[15:0]#, DINV[0]#
Output
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Description
Data Bus Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
.
Associated Strobe
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
95

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