Intel P8700 - Core 2 Duo Processor Datasheet page 75

Package Mechanical Specifications and Pin Information
Table 17.
Pin # Pin Name
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21 BSEL[2]
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5 STPCLK#
D6 PWRGOOD
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
Datasheet
Pin # Listing
Signal Buffer
Type
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
DBR# CMOS
CMOS
VSS Power/Other
TEST1 Test
TEST3 Test
VSS Power/Other
VCCA Power/Other
VSS Power/Other
RSVD Reserved
RSVD Reserved
VSS Power/Other
CMOS
CMOS
SLP# CMOS
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
VCC Power/Other
VCC Power/Other
VSS Power/Other
IERR# Open Drain
Table 17.
Directi
Pin # Pin Name
on
PROCHOT
D21
D22 RSVD
D23 VSS
D24 DPWR#
D25 TEST2
D26 VSS
E1 DBSY#
E2 BNR#
E3 VSS
Output
E4 HITM#
Output
E5 DPRSTP#
E6 VSS
E7 VCC
E8 VSS
E9 VCC
E10 VCC
E11 VSS
E12 VCC
E13 VCC
E14 VSS
Input
E15 VCC
Input
E16 VSS
Input
E17 VCC
E18 VCC
E19 VSS
E20 VCC
E21 VSS
E22 D[0]#
E23 D[7]#
E24 VSS
E25 D[6]#
E26 D[2]#
Output
F1 BR0#
Pin # Listing
Signal Buffer Directi
Type
Input/
Open Drain
# Output
Reserved
Power/Other
Input/
Common Clock
Output
Test
Power/Other
Input/
Common Clock
Output
Input/
Common Clock
Output
Power/Other
Input/
Common Clock
Output
CMOS Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/
Source Synch
Output
Input/
Source Synch
Output
Power/Other
Input/
Source Synch
Output
Input/
Source Synch
Output
Input/
Common Clock
Output
on
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