Table Of Contents - Intel P8700 - Core 2 Duo Processor Datasheet

Contents
1 Introduction .............................................................................................................. 7
1.1 Terminology ....................................................................................................... 8
1.2 References ......................................................................................................... 9
2 Low Power Features ................................................................................................ 11
2.1 Clock Control and Low-Power States .................................................................... 11
2.1.1 Core Low-Power State Descriptions........................................................... 13
2.1.1.1
2.1.1.2
2.1.1.3
2.1.1.4
2.1.1.5
2.1.1.6
2.1.1.7
2.1.2 Package Low-power State Descriptions...................................................... 15
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.5
2.1.2.6
2.2 Enhanced Intel SpeedStep® Technology .............................................................. 19
2.3 Extended Low-Power States................................................................................ 20
2.4 FSB Low Power Enhancements ............................................................................ 21
2.4.1 Dynamic FSB Frequency Switching ........................................................... 21
2.4.2 Enhanced Intel® Dynamic Acceleration Technology .................................... 22
2.5 VID-x .............................................................................................................. 23
2.6 Processor Power Status Indicator (PSI-2) Signal .................................................... 23
3 Electrical Specifications ........................................................................................... 25
3.1 Power and Ground Pins ...................................................................................... 25
3.2 Decoupling Guidelines ........................................................................................ 25
3.2.1 VCC Decoupling...................................................................................... 25
3.2.2 FSB AGTL+ Decoupling ........................................................................... 25
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 25
3.3 Voltage Identification and Power Sequencing ........................................................ 26
3.4 Catastrophic Thermal Protection .......................................................................... 29
3.5 Reserved and Unused Pins.................................................................................. 29
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 29
3.7 FSB Signal Groups............................................................................................. 30
3.8 CMOS Signals ................................................................................................... 31
3.9 Maximum Ratings.............................................................................................. 31
3.10 Processor DC Specifications ................................................................................ 32
4 Package Mechanical Specifications and Pin Information .......................................... 51
4.1 Package Mechanical Specifications ....................................................................... 51
4.2 Processor Pinout and Pin List .............................................................................. 59
4.3 Alphabetical Signals Reference ............................................................................ 93
5 Thermal Specifications and Design Considerations ................................................ 101
5.1 Monitoring Die Temperature ............................................................................. 108
5.1.1 Thermal Diode ..................................................................................... 108
5.1.2 Intel® Thermal Monitor......................................................................... 109
Datasheet
Core C0 State........................................................................... 13
Core C1/AutoHALT Powerdown State ........................................... 13
Core C1/MWAIT Powerdown State ............................................... 14
Core C2 State........................................................................... 14
Core C3 State........................................................................... 14
Core C4 State........................................................................... 14
Core Deep Power Down Technology (Code Name C6) State ............ 15
Normal State............................................................................ 15
Stop-Grant State ...................................................................... 15
Stop-Grant Snoop State............................................................. 16
Sleep State .............................................................................. 16
Deep Sleep State ...................................................................... 16
Deeper Sleep State ................................................................... 17
3