Table 5.30 Ultra Dma Sender And Recipient Timing Requirements - Fujitsu MHW2040AC Product Manual

Interface

Table 5.30 Ultra DMA sender and recipient timing requirements

MODE 0 MODE 1
(in ns) (in ns)
NAME
MIN MAX MIN MAX MIN MAX MIN MAX
t 14.7 9.7
DSIC
t 4.8 4.8
DHIC
t 72.9 50.9
DVSIC
t 9 9
DVHIC
*1: The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input
STROBE with a slew rate of 0.4 V/ns rising and falling at t
*2: The parameters t and t
DVSIC DVHIC
capacitive load value. Noise that may couple onto the output signals from external sources in a normally functioning system has not
been included in these values.
Note:
All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.
5-154
MODE 2 MODE 3
(in ns) (in ns)
6.8 6.8
4.8 4.8
33.9 22.6
9 9
and t
DSIC
shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same
MODE 4 MODE 5
(in ns) (in ns)
MIN MAX MIN MAX
4.8 2.3 Recipient IC data setup time (from
data valid until STROBE edge)
(*1)
4.8 2.8 Recipient IC data hold time (from
STROBE edge until data may
become invalid) (*1)
9.5 6 Sender IC data valid setup time
(from data valid until STROBE
edge) (*2)
9 6 Sender IC data valid hold time
(from STROBE edge until data
may become invalid) (*2)
timing (as measured through 1.5V).
DHIC
COMMENT
C141-E258