Page 1 C141-E250-01EN MHW2080AT, MHW2060AT, MHW2040AT DISK DRIVES PRODUCT MANUAL...
Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Page 3: Revision History
Revision History (1/1) Revised section (*1) Edition Date Details (Added/Deleted/Altered) 2006-08-31 *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E250...
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Page 5 Preface This manual describes MHW2080AT, MHW2060AT, MHW2040AT model of the MHW Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems.
Page 6: Operating Environment
Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does...
Page 7 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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Page 9: Important Alert Items
Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.
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Page 11: Manual Organization
Manual Organization • Device Overview MHW2080AT, MHW2060AT, • Device Configuration MHW2040AT • Installation Conditions • Theory of Device Operation DISK DRIVES • Interface PRODUCT MANUAL (C141-E250) • Operations <This manual> • Maintenance and Diagnosis MHW2080AT, MHW2060AT, • Removal and Replacement Procedure...
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Page 13: Table Of Contents
Contents CHAPTER 1 Device Overview ............... 1-1 1.1 Features ......................1-2 1.1.1 Functions and performance ..............1-2 1.1.2 Adaptability ..................... 1-2 1.1.3 Interface....................1-3 1.2 Device Specifications ..................1-4 1.2.1 Specifications summary................1-4 1.2.2 Model and product number ..............1-5 1.3 Power Requirements...................1-6 1.4 Environmental Specifications................1-9 1.5 Acoustic Noise ....................1-10 1.6 Shock and Vibration ..................
Page 14 Contents 2.2.3 2 drives connection..................2-4 CHAPTER 3 Installation Conditions..............3-1 3.1 Dimensions ......................3-2 3.2 Mounting ......................3-3 3.3 Cable Connections....................3-8 3.3.1 Device connector ..................3-8 3.3.2 Cable connector specifications ..............3-9 3.3.3 Device connection ...................3-9 3.3.4 Power supply connector (CN1) .............3-10 3.4 Jumper Settings....................3-10 3.4.1 Location of setting jumpers ..............3-10 3.4.2 Factory default setting ................3-11 3.4.3 Master drive-slave drive setting.............3-11...
Page 15 Contents 4.6 Read/write Circuit ....................4-9 4.6.1 Read/write preamplifier (PreAMP) ............4-9 4.6.2 Write circuit.....................4-9 4.6.3 Read circuit.................... 4-10 4.6.4 Digital PLL circuit.................4-11 4.7 Servo Control ....................4-12 4.7.1 Servo control circuit ................4-12 4.7.2 Data-surface servo format ..............4-15 4.7.3 Servo frame format................4-17 4.7.4 Actuator motor control ................4-18 4.7.5 Spindle motor control................4-19 CHAPTER 5 Interface ..................
Page 16 Contents (11) IDLE IMMEDIATE (X’95’ or X’E1’) / UNLOAD IMMEDIATE (X’95’ or X’E1’) ........... 5-34 (12) STANDBY (X’96’ or X’E2’) ............5-36 (13) IDLE (X’97’ or X’E3’) ..............5-37 (14) CHECK POWER MODE (X’98’ or X’E5’) ......... 5-39 (15) SLEEP (X’99’ or X’E6’) .............. 5-40 (16) SMART (X’B0) ................
Page 17 Contents (44) SET MAX ADDRESS EXT (X’37’): Option (customizing)..............5-118 (45) WRITE MULTIPLE EXT (X’39’): Option (customizing)..5-120 (46) WRITE DMA FUA EXT (X’3D’): Option (customizing) ..5-121 (47) WRITE LOG EXT (X’3F’) [Optional command (Customize)]................5-122 (48) READ VERIFY SECTOR(S) EXT (X’42): Option (customizing)..............
Page 18 Contents 6.1.2 Response to hardware reset ..............6-3 6.1.3 Response to software reset...............6-5 6.1.4 Response to diagnostic command............6-6 6.2 Power Save ......................6-7 6.2.1 Power save mode ..................6-7 6.2.2 Power commands..................6-9 6.3 Defect Processing ....................6-9 6.3.1 Spare area ....................6-9 6.3.2 Alternating processing for defective sectors..........6-10 6.4 Read-ahead Cache ....................6-12 6.4.1 DATA buffer structure ................6-12 6.4.2 Caching operation..................6-13...
Page 19 Contents Illustrations Figures Figure 1.1 Permissible range of +5V rise slope .............1-6 Figure 1.2 The example of negative voltage waveform at +5 V when power is turned off................1-7 Figure 1.3 Current fluctuation (Typ.) at +5 V when power is turned on ....1-9 Figure 2.1 Disk drive outer view ................2-2 Figure 2.2 1 drive system configuration ..............
Page 20 Contents Figure 5.1 Interface signals ..................5-2 Figure 5.2 Execution example of READ MULTIPLE command ......5-63 Figure 5.3 READ SECTOR(S) COMMAND protocol........5-130 Figure 5.4 Protocol for command abort .............5-131 Figure 5.5 WRITE SECTOR(S) command protocol .........5-133 Figure 5.6 Protocol for the command execution without data transfer ....5-135 Figure 5.7 Normal DMA data transfer ...............5-136 Figure 5.8 Ultra DMA termination with pull-up or pull-down ......5-148 Figure 5.9 PIO data transfer timing..............5-149...
Page 21 Contents Tables Table 1.1 Specifications..................1-4 Table 1.2 Examples of model names and product numbers........1-5 Table 1.3 Current and power dissipation ............... 1-8 Table 1.4 Environmental specifications..............1-9 Table 1.5 Acoustic noise specification ..............1-10 Table 1.6 Shock and vibration specification............1-10 Table 1.7 Advanced Power Management ............1-14 Table 3.1 Surface temperature measurement points and standard values....3-5 Table 3.2 Cable connector specifications ..............3-9 Table 5.1 Signal assignment on the interface connector........5-3...
Page 22 Contents Table 5.27 Command code and parameters ............5-127 Table 5.28 Recommended series termination for Ultra DMA ......5-148 Table 5.29 Ultra DMA data burst timing requirements ........5-152 Table 5.30 Ultra DMA sender and recipient timing requirements.....5-154 xviii C141-E250...
Page 23: Chapter 1 Device Overview
CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management (APM) Overview and features are described in this chapter, and specifications and power requirement are described.
Page 24: Features
The disk drive can record up to 80 GB (formatted) on one disk using the RLL recording method and 30 recording zone technology. The disk drive has a formatted capacity of 80 GB (MHW2080AT), 60 GB (MHW2060AT) and 40 GB (MHW2040AT) respectively.
Page 25: Interface
1.1 Features (3) Low noise and vibration In Ready status (while the device is waiting for any commands), the Sound Power level of the disk drives in idle mode is 1.5 B. The Sound Pressure level is 16 dB, as measured 0.3 m from the drive in Idle mode. (4) High resistance against shock The Load/Unload mechanism is highly resistant against non-operation shock up to 8820 m/s...
Page 26: Device Specifications
This feature reduces the access time at writing. 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives. Table 1.1 Specifications (1 of 2) MHW2080AT MHW2060AT MHW2040AT Format Capacity (*1) 80 GB...
Page 27: Model And Product Number
CHS mode has been selected using the BIOS setup utility on the host. Table 1.1 Specifications (2 of 2) Model Capacity No. of Cylinder No. of Heads No. of Sectors MHW2080AT 8.45 GB 16,383 MHW2060AT 8.45 GB 16,383 MHW2040AT 8.45 GB 16,383 1.2.2 Model and product number...
Page 28: Power Requirements
Device Overview 1.3 Power Requirements (1) Input Voltage • + 5 V ± 5 % (2) Ripple +5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz (3) Slope of an input voltage at rise The following figure shows the restriction of the slope which is +5 V input voltage at rise.
Page 29: Figure 1.2 The Example Of Negative Voltage Waveform At +5 V When
1.3 Power Requirements (4) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned off and, a thing with no ringing. Permissible level: −0.2 V Time [ms] Figure 1.2 The example of negative voltage waveform at +5 V when power is turned off C141-E250...
Page 30: Table 1.3 Current And Power Dissipation
40 mA 0.20 W Sleep 20 mA 0.1 W Energy 0.0063 W/GB (rank D / MHW2080AT) Efficiency (*4) — 0.0083 W/GB (rank D / MHW2060AT) 0.0125 W/GB (rank D / MHW2040AT) Maximum current at starting spindle motor. Current and power level when the operation (command) that accompanies a transfer of 63 sectors is executed 3 times in 100 ms Power requirements reflect typical values for +5 V power.
Page 31: Environmental Specifications
1.4 Environmental Specifications (6) Current fluctuation (Typ.) at +5 V when power is turned on Figure 1.3 Current fluctuation (Typ.) at +5 V when power is turned on 1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.4 Environmental specifications Item Specification Temperature...
Page 32: Acoustic Noise
Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification (typical) • Idle mode (DRIVE READY) Sound Power 1.5 B Sound Pressure (at 0.3m) 16 dB Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.
Page 33: Reliability
1.7 Reliability 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20 % or less of power-on time Temperature 5 to 60 °C (DE surface) Humidity 8 to 90 % (ambient) But humidity bulb temperature 29 °C or less MTBF is defined as follows:...
Page 34: Error Rate
Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 1 time when reading...
Page 35: Recommended Power-Off Sequence
1.11 Advanced Power Management (APM) Emergency Unload other than Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Unload cannot be executed. Therefore, the number of Emergency other than Unload is specified.
Page 36: Table 1.7 Advanced Power Management
Device Overview Active Idle: The head is in a position of extreme inner in disk medium. (VCM Lock) Low Power Idle: The head is unloaded from disk. The spindle motor rotates. Standby: The spindle motor stops. In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle."...
Page 37: Chapter 2 Device Configuration
CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E250...
Page 38: Device Configuration
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motor, actuator, and a circulating air filter. Figure 2.1 Disk drive outer view (1) Disk The outer diameter of the disk is 65 mm.
Page 39: System Configuration
44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s). 2.2.2 1 drive connection MHW2080AT MHW2060AT MHW2040AT Figure 2.2 1 drive system configuration...
Page 40: Drives Connection
Device Configuration 2.2.3 2 drives connection MHW2080AT (Host adaptor) MHW2060AT MHW2040AT MHW2080AT MHW2060AT MHW2040AT Note: When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed. Figure 2.3 2 drives configuration HA (host adaptor) consists of address decoder, driver, and receiver.
Page 41: Chapter 3 Installation Conditions
CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.
Page 42: Dimensions
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions C141-E250...
Page 43: Mounting
3.2 Mounting 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation The disk drives can be mounted in any direction. (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG.
Page 44: Figure 3.3 Location Of Breather
Installation Conditions Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.3. For breather hole of Figure 3.3, at least, do not allow its around φ 3 to block.
Page 45: Figure 3.4 Surface Temperature Measurement Points
3.2 Mounting (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 °C.
Page 46: Figure 3.5 Service Area
Installation Conditions (5) Service area Figure 3.5 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.5 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.
Page 47: Figure 3.6 Handling Cautions
3.2 Mounting General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically Do not drop.
Page 48: Cable Connections
Installation Conditions 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.7 Connector locations C141-E250...
Page 49: Cable Connector Specifications
3.3 Cable Connections 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 supply cable (44-pin type) (44-pin type) For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.
Page 50: Power Supply Connector (Cn1)
Installation Conditions 3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumpers to select drive configuration and functions.
Page 51: Factory Default Setting
3.4 Jumper Settings 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. Open Figure 3.11 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Short Open...
Page 52: Csel Setting
Installation Conditions 3.4.4 CSEL setting Figure 3.13 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.13 CSEL setting Figure 3.14 and 3.15 show examples of cable selection using unique interface cables.
Page 53: Power Up In Standby Setting
3.4 Jumper Settings drive drive Figure 3.15 Example (2) of cable select 3.4.5 Power up in standby setting When pin C is grounded, the drive does not spin up at power on. C141-E250 3-13...
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Page 55: Chapter 4 Theory Of Device Operation
CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Page 56: Outline
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).
Page 57: Air Filter
4.3 Circuit Configuration 4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.
Page 58: Figure 4.1 Power Supply Configuration
Theory of Device Operation (4) Controller circuit Major functions are listed below. • ATA interface control and data transfer control • Data buffer management • Sector format control • Defect management • ECC control • Error recovery and self-diagnosis 5.0V S-DRAM 3.3V 3.3V...
Page 59: Figure 4.2 Circuit Configuration
4.3 Circuit Configuration ATA Interface MCU & HDC & RDC Data Buffer SDRAM Shock Sensor Resonator SP Motor Thermistor R/W Pre-Amp HEAD Media Figure 4.2 Circuit configuration C141-E250...
Page 60: Power-On Sequence
Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
Page 61: Self-Calibration
4.5 Self-calibration 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.
Page 62: Execution Timing Of Self-Calibration
Theory of Device Operation 4.5.2 Execution timing of self-calibration Self-calibration is performed once when power is turned on. After that, the disk drive does not perform self-calibration until it detects an error. That is, self-calibration is performed each time one of the following events occur: •...
Page 63: Read/Write Circuit
4.6 Read/write Circuit 4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) PreAMP equips a read preamplifier and a write current switch, that sets the bias current to the MR device and the current in writing.
Page 64: Read Circuit
Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This signal is converted into the read data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit.
Page 65: Digital Pll Circuit
4.6 Read/write Circuit (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.
Page 66: Servo Control
Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
Page 67 4.7 Servo Control (1) Microprocessor unit (MPU) The MPU executes startup of the spindle motor, movement to the reference cylinder, seek to the specified cylinder, and calibration operations. The main internal operations of the MPU are shown below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied.
Page 68 Theory of Device Operation (6) Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor. (7) VCM current sense resistor (CSR) This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.
Page 69: Data-Surface Servo Format
4.7 Servo Control 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.
Page 70: Figure 4.7 Physical Sector Servo Configuration On Disk Surface
Theory of Device Operation Servo frame (172 servo frames per revolution) Data area expand CYLn CYLn – 1 (n: even number) CYLn + 1 Diameter direction W/R Recovery W/R Recovery W/R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code EVEN1...
Page 71: Servo Frame Format
4.7 Servo Control 4.7.3 Servo frame format As the servo information, the IDD uses the phase signal servo generated from the gray code and servo EVEN and ODD. This servo information is used for positioning operation of radius direction and position detection of circumstance direction.
Page 72: Actuator Motor Control
Theory of Device Operation 4.7.4 Actuator motor control The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.
Page 73: Spindle Motor Control
(called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
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Page 75: Chapter 5 Interface
CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E250...
Page 76: Physical Interface
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DATA 0-15: DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...
Page 77: Signal Assignment On The Connector
5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL PUS- ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...
Page 78 Interface [Signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...
Page 79 5.1 Physical Interface [Signal] [I/O] [Description] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.
Page 80: Logical Interface
Interface [Signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.
Page 81: I/O Registers
5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2 shows the coding address and the function of I/O registers.
Page 82: Command Block Registers
Interface Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively. If the LBA mode is specified with 48-bit address information, the Cylinder High, Cylinder Low, Sector Number registers are set twice.
Page 83 5.2 Logical Interface - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred. [Diagnostic code] X’01’: No Error Detected.
Page 84 Interface (5) Sector Number register (X’1F3’) The contents of this register indicate the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command. Under the LBA mode, this register indicates LBA bits 7 to 0.
Page 85 5.2 Logical Interface (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.). Bit 7 Bit 6 Bit 5...
Page 86 Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).
Page 87: Control Block Registers
5.2 Logical Interface (10) Command register (X’1F7’) The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately. Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written.
Page 88: Host Commands
Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRST nIEN - Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command.
Page 89: Table 5.3 Command Code And Parameters
5.3 Host Commands Table 5.3 Command code and parameters (1 of 2) COMMAND CODE (Bit) PARAMETER USED COMMAND NAME FR SC SN CY DH RECALIBRATE READ SECTOR(S) WRITE SECTOR(S) WRITE VERIFY READ VERIFY SECTOR(S) SEEK EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS DOWNLOAD MICROCODE STANDBY IMMEDIATE...
Page 90 Interface Table 5.3 Command code and parameters (2 of 2) COMMAND CODE (Bit) PARAMETER USED COMMAND NAME FR SC SN CY DH FLUSH CACHE WRITE BUFFER IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SECURITY SET PASSWORD SECURITY UNLOCK SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY DISABLE...
Page 91 5.3 Host Commands Note: READ LONG (0x22) command/WRITE LONG (0x33) command became a unsupport from the MHW2xxxAT series. Notes: Features Register CY: Cylinder Registers Sector Count Register DH: Drive/Head Register SN: Sector Number Register Retry at error 1 = Without retry 0 = With retry Necessary to set parameters Necessary to set parameters under the LBA mode.
Page 92: Command Descriptions
Interface 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) (DH) Head No.
Page 93 5.3 Host Commands SC: Sector Count register x, xx: Do not care (no necessary to set) Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
Page 94: Recalibrate (X'10' To X'1F')
Interface (1) RECALIBRATE (X’10’ to X’1F’) This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the BSY bit, and generates an interrupt.
Page 95: Read Sector(S) (X'20' Or X'21')
5.3 Host Commands (2) READ SECTOR(S) (X’20’ or X’21’) This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified from 1 to 256 sectors. To specify 256 sectors reading, ‘00’...
Page 96 Interface (R: Retry) At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 97: Write Sector(S) (X'30' Or X'31')
5.3 Host Commands (3) WRITE SECTOR(S) (X’30’ or X’31’) This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified from 1 to 256 sectors.
Page 98 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 99: Write Verify (X'3C')
5.3 Host Commands (4) WRITE VERIFY (X’3C’) This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.
Page 100: Read Verify Sector(S) (X'40' Or X'41')
Interface (5) READ VERIFY SECTOR(S) (X’40’ or X’41’) This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system. After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt.
Page 101: Seek (X'70' To X'7F')
5.3 Host Commands (6) SEEK (X’70’ to X’7F’) This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.
Page 102: Execute Device Diagnostic (X'90')
Interface (7) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.
Page 103 5.3 Host Commands Note: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting contents) (CM) Head No. /LBA [MSB] (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information Head No.
Page 104: Initialize Device Parameters (X'91')
Interface (8) INITIALIZE DEVICE PARAMETERS (X’91’) The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters.
Page 105: Download Microcode (X'92')
5.3 Host Commands (9) DOWNLOAD MICROCODE (X’92’) At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) Sector count (15-8) (SC) Sector count (7-0) (FR) Subcommand code At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL)
Page 106: Table 5.5 Operation Of Download Microcode
Interface Table 5.5 Operation of DOWNLOAD MICROCODE Host Command Movement of device Subcommand code Sector count Data transfer Microcode rewriting execution (FR Reg) (SN, SC Reg) 0000h Rewriting execution reservation xxxxh It is. Rewriting execution reservation 0000h Execution. ** xxxxh It is.
Page 107: Standby Immediate (X'94' Or X'e0')
5.3 Host Commands (10) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the APS timer function. At command issuance (I/O registers setting contents) (CM) X’94’...
Page 108: Idle Immediate (X'95' Or X'e1') / Unload Immediate (X'95' Or X'e1')
Interface (11) IDLE IMMEDIATE (X’95’ or X’E1’) / UNLOAD IMMEDIATE (X’95’ or X’E1’) • Default function Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt.
Page 109 5.3 Host Commands Even if the device executes reading look-ahead operation or executes writing operation, the device unloads the head(s) to the ramp position as soon as possible when received the IDLE IMMEDIATE command with the Unload Feature. When the writing operation is stopped, the device keeps the unwritten data. And, the device keeps the unloaded state until receiving a Soft / Hard Reset, or a new command except IDLE IMMEDIATE command with the Unload Feature.
Page 110: Standby (X'96' Or X'e2')
Interface (12) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. If the device has already spun down, the spin-down sequence is not implemented.
Page 111: Idle (X'97' Or X'e3')
5.3 Host Commands (13) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates interrupt even if the device has not fully entered the idle mode.
Page 112 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-38 C141-E250...
Page 113: Check Power Mode (X'98' Or X'e5')
5.3 Host Commands (14) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value.
Page 114: Sleep (X'99' Or X'e6')
Interface (15) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.
Page 115: Smart (X'b0)
5.3 Host Commands (16) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued. Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register).
Page 116: Table 5.7 Features Register Values (Subcommands) And Functions
Interface Table 5.7 Features register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART READ DATE: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
Page 117 5.3 Host Commands Table 5.7 Features register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART READ LOG: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.
Page 118 Interface Table 5.7 Features register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART RETURN STATUS: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.
Page 119 5.3 Host Commands At command issuance (I-O registers setting contents) (CM) (DH) (CH) Key (C2h) (CL) Key (4Fh) (SN) (SC) (FR) Subcommand At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h/2Ch) (CL) Key-failure prediction status (4Fh/F4h) (SN) (SC) (ER)
Page 120: Table 5.8 Format Of Device Attribute Value Data
Interface Table 5.8 Format of device attribute value data Byte Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far 07 to 0C Raw attribute value Reserved 0E to 169 Attribute 2 to (The format of each attribute value is the same as attribute 30...
Page 121 5.3 Host Commands • Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same.
Page 122 Interface • Status Flag Meaning If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value. If this bit is 1 (0), it indicates the attribute only updated by an on- line test (off-line test).
Page 123: Table 5.10 Off-Line Data Collection Status
5.3 Host Commands Table 5.10 Off-line data collection status Status Byte Meaning 00h or 80h Off-line data acquisition is not executed. 02h or 82h Off-line data acquisition has ended without an error. 04h or 84h Off-line data acquisition is interrupted by a command from the host. 05h or 85h Off-line data acquisition has ended before completion because of a command from the host.
Page 124: Table 5.12 Off-Line Data Collection Capability
Interface • Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off- line data collection capability is 0, it indicates that off-line data collection is not supported. Table 5.12 Off-line data collection capability Meaning If this bit is 1, it indicates that the SMART EXECUTE OFF- LINE IMMEDATE sub-command (FR register = D4h) is...
Page 125: Table 5.14 Error Logging Capability
5.3 Host Commands • Error logging capability Table 5.14 Error logging capability Meaning If this bit is 1, it indicates that the drive error logging function is supported. 1 to 7 Reserved bits • Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.
Page 126 Interface • SMART error logging If the device detects an unrecoverable error during execution of a command received from the host, the device registers the error information in the SMART Summary Error Log (see Table 5.16) and the SMART Comprehensive Error Log (see Table 5.17), and saves the information on media.
Page 127: Table 5.16 Data Format Of Smart Summary Error Log
5.3 Host Commands Table 5.16 Data format of SMART Summary Error Log Byte Item Version of this function Pointer for the latest "Error Log Data Structure" 02 to 0D First command data structure 0E to 19 Second command data structure 1A to 25 Third command data structure 26 to 31...
Page 128: Table 5.17 Data Format Of Smart Comprehensive Error Log
Interface • Command data structure Indicates the command received when an error occurs. • Error data structure Indicates the status register when an error occurs. • Total number of drive errors Indicates total number of errors registered in the error log. •...
Page 129: Table 5.18 Smart Self-Test Log Data Format
5.3 Host Commands • SMART self-test The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self-test. When the self-test is completed, the device saves the SMART self-test log to the disk medium.
Page 130: Table 5.19 Selective Self-Test Log Data Structure
Interface Table 5.19 Selective self-test log data structure Offset Description Initial 00h, 01h 01h, 00h Data Structure Revision Number 02h...09h Starting LBA 00h...00h Test Span 1 0Ah...11h Ending LBA 00h...00h 12h...19h Starting LBA 00h...00h Test Span 2 1Ah...21h Ending LBA 00h...00h 22h...29h Starting LBA...
Page 131: Table 5.20 Selective Self-Test Feature Flags
5.3 Host Commands • Feature Flags Table 5.20 Selective self-test feature flags Description Vendor specific (unused) When set to one, perform off-line scan after selective test Vendor specific (unused) When set to one, off-line scan after selective test is pending. When set to one, off-line scan after selective test is active.
Page 132: Device Configuration (X'b1')
Interface (17) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these Features register values. If this command sets with the reserved value of Features register, an aborted error is posted.
Page 133 5.3 Host Commands • DEVICE CONFIGURATION RESTORE (FR = C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command.
Page 134 Interface If the restriction of Multiword DMA modes or Ultra DMA modes is executed, a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued. When the Automatic Acoustic Management function is assumed to be unsupported, Automatic Acoustic Management is prohibited beforehand by SET FEATURES command (FR=C2h).
Page 135: Table 5.21 Device Configuration Identify Data Structure
5.3 Host Commands Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure (1 of 2) Word Value Content X'0002' Data structure revision X'0007' Multiword DMA modes supported Reflected in IDENTIFY information "WORD63". Bit 15-3: Reserved Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0:...
Page 136 Interface Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure (2 of 2) Word Value Content 8-254 X'0000' Reserved X'xxA5' Integrity word. Bits 15:8 contains the data structure checksum that is the two's complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7:0 of word 255.
Page 137: Read Multiple (X'c4')
5.3 Host Commands (18) READ MULTIPLE (X’C4’) The READ MULTIPLE Command performs the same as the READ SECTOR(S) Command except that when the device is ready to transfer data for a block of sectors, and enters the interrupt pending state only before the data transfer for the first sector of the block sectors.
Page 138 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)
Page 139: Write Multiple (X'c5')
5.3 Host Commands (19) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
Page 140 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) (ER) Error information...
Page 141: Set Multiple Mode (X'c6')
5.3 Host Commands (20) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands is also specified by the SET MULTIPLE MODE command.
Page 142 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) Sector count/block (ER) Error information 5-68 C141-E250...
Page 143: Read Dma (X'c8' Or X'c9')
5.3 Host Commands (21) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...
Page 144 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 145: Write Dma (X'ca' Or X'cb')
5.3 Host Commands (22) WRITE DMA (X’CA’ or X’CB’) This command operates similarly to the WRITE SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...
Page 146 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 147: Read Buffer (X'e4')
5.3 Host Commands (23) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
Page 148: Flush Cache (X'e7')
Interface (24) FLUSH CACHE (X’E7’) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred. The device performs every error recovery so that the data are read correctly.
Page 149: Write Buffer (X'e8')
5.3 Host Commands (25) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data.
Page 150: Identify Device (X'ec')
Interface (26) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information from the device. Upon receipt of this command, the drive sets the BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and generates an interrupt.
Page 151: Identify Device Dma (X'ee')
5.3 Host Commands (27) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
Page 152: Table 5.22 Information To Be Read By Identify Device Command
Interface Table 5.22 Information to be read by IDENTIFY DEVICE command (1 of 2) Word Value Description X’045A’ General Configuration *1 X’3FFF’ Number of Logical cylinders *2 X’xxxx’ Detailed Configuration *3 X’10’ Number of Logical Heads *2 X’0000’ Undefined X’3F’ Number of Logical sectors per Logical track *2 X’0000’...
Page 153 5.3 Host Commands Table 5.22 Information to be read by IDENTIFY DEVICE command (2 of 2) Word Value Description X’0078’ Minimum multiword DMA transfer cycle time per word: 120 [ns] X’0078’ Manufacturer’s recommended DMA transfer cycle time: 120 [ns] X’00F0’ Minimum PIO transfer cycle time without IORDY flow control: 240 [ns] X’0078’...
Page 154 Bit 2: IDENTIFY DEVICE Valid = 0 Bit 1-0: Reserved *2 Word 1, 3, 6, 60-61 Word MHW2080AT MHW2060AT MHW2040AT X ' 3FFF ' X ' 3FFF ' X ' 3FFF ' X ' 10 ' X ' 10 '...
Page 155 5.3 Host Commands *5 Word 50: Device capability Bit 15: Bit 14: Bit 13 to 1 Reserved Bit 0 Standby timer value '1' = Standby timer value of the device is the smallest value. *6 Word 51: PIO data transfer mode Bit 15-8: PIO data transfer mode X’02’=PIO mode 2...
Page 156 Interface *10 Word 64: Advance PIO transfer mode support status Bit 15-8: Reserved Bit 7-0: Advance PIO transfer mode Bit 1: 1 = Mode 4 (Bit 0 = '1') Bit 0: 1 = Mode 3 *11 WORD 80 Bit 15-8: Reserved Bit 7: 1 = ATA/ATAPI-7 supported...
Page 157 5.3 Host Commands *13 WORD 83 Bit 15: Bit 14: Bit 13: * '1' = FLUSH CACHE EXT command supported. Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10:* '1' = 48 bit LBA feature set.
Page 158 Interface Bit 5: * '1' = Supports the General Purpose Logging feature set Bit 4: '1' = Supports the Streaming feature set Bit 3-2: Reserved Bit 1: '1' = Supports the SMART SELF-TEST. Bit 0: '1' = Supports the SMART Error Logging. *: Option (customizing) *15 WORD 85 Bit 15:...
Page 159 5.3 Host Commands *16 WORD 86 Bit 15-14: Reserved Bit 13: * '1' = FLUSH CACHE EXT command supported. Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10: * '1' = 48 bit LBA feature set.
Page 160 Bit 1: '1' = Supports the Mode 1 Bit 0: '1' = Supports the Mode 0 *19 WORD 89 (Value × 2 minutes) MHW2080AT = X'28': 80 minutes MHW2060AT = X'1E': 60 minutes MHW2040AT = X'14': 40 minutes *20 WORD 93...
Page 161 5.3 Host Commands Bit 11: '1' = Device asserts PDIAG-. Bit 10, 9: Method for deciding the device No. of Device 1. '00' = Reserved '01' = Using a jumper. '10' = Using the CSEL signal. '11' = Other method. Bit 8: = '1' (In the case of device 1) Bits 7-0:...
Page 162 Interface *23 WORD 128 Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-6: Reserved Bit 5: '1' = Enhanced security erase supported Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2: '1' = Security locked Bit 1: '1' = Security enabled...
Page 163: Set Features (X'ef')
5.3 Host Commands (28) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register.
Page 164 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or *1~3 (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information *1) Data Transfer Mode The host sets X’03’...
Page 165 5.3 Host Commands Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) 01000 101 (X’45’: Mode 5)
Page 166 Interface *3) Automatic Acoustic Management (AAM) The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h, and then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets.
Page 167: Security Set Password (X'f1')
5.3 Host Commands (29) SECURITY SET PASSWORD (X’F1’) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.24 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
Page 168 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-94 C141-E250...
Page 169: Security Unlock(X'f2')
5.3 Host Commands (30) SECURITY UNLOCK(X’F2’) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.26 to the device. Operation of the device varies as follows depending on whether the host specifies the master password. •...
Page 170 Interface At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-96 C141-E250...
Page 171: Security Erase Prepare (X'f3')
5.3 Host Commands (31) SECURITY ERASE PREPARE (X’F3’) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
Page 172: Security Erase Unit (X'f4')
Interface (32) SECURITY ERASE UNIT (X’F4’) This command erases all user data. This command also invalidates the user password and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set.
Page 173: Security Freeze Lock (X'f5')
5.3 Host Commands (33) SECURITY FREEZE LOCK (X’F5’) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE. • SECURITY SET PASSWORD •...
Page 174 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-100 C141-E250...
Page 175: Security Disable Password (X'f6')
5.3 Host Commands (34) SECURITY DISABLE PASSWORD (X’F6’) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.
Page 176 Interface At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-102 C141-E250...
Page 177: Read Native Max Address (X'f8')
5.3 Host Commands (35) READ NATIVE MAX ADDRESS (X’F8’) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers.
Page 178: Set Max (X'f9')
Interface (36) SET MAX (X’F9’) SET MAX features register values Value Command Obsolete SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK 05h - FFh Reserved • SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command.
Page 179 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
Page 180 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Password information Words Contents Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved • SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
Page 181 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information • SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.
Page 182 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information • SET MAX FREEZE LOCK (FR = 04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
Page 183 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E250 5-109...
Page 184: Read Sector(S) Ext (X'24'): Option (Customizing)
Interface (37) READ SECTOR(S) EXT (X’24’): Option (customizing) • Description This command is the extended command of the READ SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 185: Read Dma Ext (X'25'): Option (Customizing)
5.3 Host Commands (38) READ DMA EXT (X’25’): Option (customizing) • Description This command is the extended command of the READ DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 186: Read Native Max Address Ext (X'27'): Option (Customizing)
Interface (39) READ NATIVE MAX ADDRESS EXT (X’27’): Option (customizing) • Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1.
Page 187: Read Multiple Ext (X'29'): Option (Customizing)
5.3 Host Commands (40) READ MULTIPLE EXT (X’29’): Option (customizing) • Description This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 188: Read Log Ext (X'2F') [Optional Command (Customize)]
Interface (41) READ LOG EXT (X'2F') [Optional command (Customize)] • Description This command reads data from the general-purpose log of a device. The general- purpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. The types of logs available depend on the customize operation.
Page 189 5.3 Host Commands Log address: Log number of the log to be read Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be read from the specified log If the device does not support this command, the device shall return the Command Aborted error.
Page 190: Write Sector(S) Ext (X'34'): Option (Customizing)
Interface (42) WRITE SECTOR(S) EXT (X’34’): Option (customizing) • Description This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 191: Write Dma Ext (X'35'): Option (Customizing)
5.3 Host Commands (43) WRITE DMA EXT (X’35’): Option (customizing) • Description This command is the extended command of the WRITE DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 192: Set Max Address Ext (X'37'): Option (Customizing)
Interface (44) SET MAX ADDRESS EXT (X’37’): Option (customizing) • Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode. The address information specified with this command is set in words 1, 54, 57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response.
Page 193 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) P SET MAX LBA (47-40) (CH) C SET MAX LBA (23-16) (CL) P SET MAX LBA (39-32) (CL) C SET MAX LBA (15-8) (SN) P SET MAX LBA (31-24) (SN) C SET MAX LBA (7-0) (SC) P...
Page 194: Write Multiple Ext (X'39'): Option (Customizing)
Interface (45) WRITE MULTIPLE EXT (X’39’): Option (customizing) • Description This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 195: Write Dma Fua Ext (X'3D'): Option (Customizing)
5.3 Host Commands (46) WRITE DMA FUA EXT (X’3D’): Option (customizing) • Description The WRITE DMA FUA EXT command has the difference that reports on status after write to media is completed regardless of the setting of present Write cache though WRITE DMA EXT command and basic operation are the same.
Page 196: Write Log Ext (X'3F') [Optional Command (Customize)]
Interface (47) WRITE LOG EXT (X’3F’) [Optional command (Customize)] • Description This command writes data to the general-purpose log of a device. The general- purpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. However, some of these logs are read-only logs.
Page 197 5.3 Host Commands Log address: Log number of the log to be written Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be written to the specified log If the device does not support this command, the device shall return the Command Aborted error.
Page 198: Read Verify Sector(S) Ext (X'42): Option (Customizing)
Interface (48) READ VERIFY SECTOR(S) EXT (X’42): Option (customizing) • Description This command is the extended command of the READ VERIFY SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 199: Write Multiple Fua Ext (X'ce'): Option (Customizing)
5.3 Host Commands (49) WRITE MULTIPLE FUA EXT (X’CE’): Option (customizing) • Description The WRITE MULTIPLE FUA EXT command has the difference that reports on status after write to media is completed regardless of the setting of present Write cache though WRITE MULTIPLE EXT command and basic operation are the same.
Page 200: Flush Cache Ext (X'ea'): Option (Customizing)
Interface (50) FLUSH CACHE EXT (X’EA’): Option (customizing) • Description This command executes the same operation as the Flush Cache command (E7h) but only LBA = 1 can be specified. • Error reporting conditions This command is issued with LBA = 0. (ST = 51h, ER= 10h: Aborted) At command issuance (I/O registers setting contents) (CM) (DH)
Page 201: Error Posting
5.3 Host Commands 5.3.3 Error posting Table 5.27 lists the defined errors that are valid for each command. Table 5.27 Command code and parameters (1 of 2) Error Register (X '1F1') Status Register (X '1F7') COMMAND NAME ICRC IDNF ABRT TK0NF DRDY RECALIBRATE...
Page 202 Interface Table 5.27 Command code and parameters (2 of 2) Error Register (X '1F1') Status Register (X '1F7') COMMAND NAME ICRC IDNF ABRT TK0NF DRDY READ SECTOR(S) EXT READ DMA EXT V *2 READ NATIVE MAX ADDRESS READ MULTIPLE EXT READ LOG EXT WRITE SECTOR(S) EXT WRITE DMA EXT...
Page 203: Command Protocol
5.4 Command Protocol 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.
Page 204: Figure 5.3 Read Sector(S) Command Protocol
Interface The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are repeated. Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit.
Page 205: Figure 5.4 Protocol For Command Abort
5.4 Command Protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
Page 206: Pio Data Transferring Commands From Host To Device
Interface 5.4.2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive. • WRITE SECTOR(S) (EXT) • WRITE VERIFY • DOWNLOAD MICROCODE • SMART WRITE LOG • DEVICE OCNFIGURATION SET •...
Page 207: Figure 5.5 Write Sector(S) Command Protocol
5.4 Command Protocol 40 ms Figure 5.5 WRITE SECTOR(S) command protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
Page 208: Commands Without Data Transfer
Interface 5.4.3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device. • RECABLIBRATE • READY VERIFY SECTOR(S) (EXT) • SEEK • EXECUTE DEVICE DIAGNOSTIC • INITIALIZE DEVICE PARAMETERS • STANDBY IMMEDIATE •...
Page 209: Other Commands
5.4 Command Protocol Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands • READ MULTIPLE (EXT) • WRITE MULTIPLE (EXT/FUA EXT) • SLEEP See the description of each command. 5.4.5 DMA data transfer commands • READ DMA (EXT) •...
Page 210: Figure 5.7 Normal Dma Data Transfer
Interface When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA data transfer 5-136 C141-E250...
Page 211: Ultra Dma Feature Set
5.5 Ultra DMA Feature Set 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host.
Page 212: Phases Of Operation
Interface Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command.
Page 213 5.5 Ultra DMA Feature Set 7) The host shall release DD (15:0) within t after asserting DMACK-. 8) The device may assert DSTROBE t after the host has asserted DMACK-. ZIORDY Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.
Page 214 Interface NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t before asserting STOP.
Page 215 5.5 Ultra DMA Feature Set 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated. 8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).
Page 216 Interface 4) If the host negates HDMARDY- within t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
Page 217: Ultra Dma Data Out Commands
5.5 Ultra DMA Feature Set 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
Page 218 Interface 5.5.4.2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements): 1) The host shall drive a data word onto DD (15:0). 2) The host shall generate an HSTROBE edge to latch the new word no sooner than t after changing the state of DD (15:0).
Page 219 5.5 Ultra DMA Feature Set 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
Page 220 Interface b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
Page 221: Ultra Dma Crc Rules
5.5 Ultra DMA Feature Set 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end...
Page 222: Series Termination Required For Ultra Dma
Interface The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.
Page 223: Timing
5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Min. Max. Unit Cycle time —...
Page 224: Multiword Data Transfer
Interface 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. CS0-/CS1- DMARQ DMACK- DIOR-/DIOW- Read DD(15:0) Write DD(15:0) Symbol Timing parameter Min. Max. Unit Pulse width of DIOR-/DIOW- — Data Access time for DIOR- —...
Page 225: Ultra Dma Data Transfer
5.6 Timing 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.23 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Page 226: Table 5.29 Ultra Dma Data Burst Timing Requirements
Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.29 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT...
Page 227 5.6 Timing Table 5.29 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN Limited interlock time (*1) Interlock time with minimum (*1) Unlimited interlock time (*1)
Page 228: Table 5.30 Ultra Dma Sender And Recipient Timing Requirements
Interface Table 5.30 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 Recipient IC data setup time (from DSIC...
Page 229: Figure 5.12 Sustained Ultra Dma Data In Burst
5.6 Timing 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC 2CYC DSTROBE at device DVHIC DVSIC DVHIC DVSIC DVHIC DD(15:0) at device DSTROBE at host DHIC DHIC DHIC DSIC...
Page 230: Figure 5.13 Host Pausing An Ultra Dma Data In Burst
Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
Page 231: Figure 5.14 Device Terminating An Ultra Dma Data In Burst
5.6 Timing 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are...
Page 232: Figure 5.15 Host Terminating An Ultra Dma Data In Burst
Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 233: Figure 5.16 Initiating An Ultra Dma Data Out Burst
5.6 Timing 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DZFS DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 234: Figure 5.17 Sustained Ultra Dma Data Out Burst
Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC HSTROBE 2CYC at host DVHIC DVHIC DVHIC DVSIC DVSIC DD(15:0) at host HSTROBE at device DHIC DSIC DHIC DSIC DHIC...
Page 235: Figure 5.18 Device Pausing An Ultra Dma Data Out Burst
5.6 Timing 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.
Page 236: Figure 5.19 Host Terminating An Ultra Dma Data Out Burst
Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 237: Figure 5.20 Device Terminating An Ultra Dma Data Out Burst
5.6 Timing 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 238: Power-On And Reset
Interface 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device]...
Page 239: Chapter 6 Operations
CHAPTER 6 Operations Device Response to the Reset Power Save Defect Processing Read-ahead Cache Write Cache C141-E250...
Page 240: Operations
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for least 500 ms to confirm presence of a slave device (device 1).
Page 241: Response To Hardware Reset
6.1 Device Response to the Reset Power on Master device Power On Reset- Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to If presence of a slave device is 500 ms. confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On Reset- BSY bit...
Page 242: Figure 6.2 Response To Hardware Reset
Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 450 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. The asserted PDIAG-signal is negated 30 seconds after it is asserted if the command is not received.
Page 243: Response To Software Reset
6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.
Page 244: Response To Diagnostic Command
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.
Page 245: Power Save
6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active.
Page 246 Operations • Upon receipt of a hard reset • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active, active idle, or low power idle mode because the access to the disk medium cannot be made immediately.
Page 247: Power Commands
6.3 Defect Processing 6.2.2 Power commands The following commands are available as power commands. • IDLE • IDLE IMMEDIATE • STANDBY • STANDBY IMMEDIATE • SLEEP • CHECK POWER MODE • SET FEATURES (APM setting) 6.3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information.
Page 248: Alternating Processing For Defective Sectors
Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Sector slip processing In this method, defective sectors are not used (thereby avoiding the effects of defects), and each defective sector is assigned to the next contiguous sector that is normal.
Page 249: Figure 6.6 Automatic Alternating Processing
6.3 Defect Processing (3) Automatic alternating processing This technology assigns a defective sector to a spare sector of a spare cylinder for alternate assignment. This device performs automatic alternating processing in the event of any of the following errors. • Automatic alternating processing is attempted for read error recovery by reaching the specified retry cycle while a read error retry is in progress.
Page 250: Read-Ahead Cache
Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead data, data on the data buffer can be transferred without accessing the disk media.
Page 251: Caching Operation
6.4 Read-ahead Cache 6.4.2 Caching operation The caching operation is performed only when the commands listed below are received. If any of the following data are stored on the data buffer, the data is sent to the host system. • All of the sector data that this command processes.
Page 252 Operations 1)-1 Any command other than the following commands is issued. (All caching- target data is invalidated.) RECALIBRATE IDLE IMMEDIATE DOWNLOAD MICROCODE DEVICE CONFIGURATION READ BUFFER WRITE BUFFER SET FEATURES SECURITY ERASE UNIT READ LOG EXT WRITE LOG EXT UNSUPPORT COMMAND (INVALID COMMAND) 1)-2 Commands that partially invalidate caching data (When data in the buffer or on media is overwritten, the overwritten data is invalidated.)
Page 253: Using The Read Segment Buffer
6.4 Read-ahead Cache 6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations. 6.4.3.1 Miss-hit In this situations, the top block of read requested data is not stored at all in the data buffer.
Page 254 Operations 6.4.3.2 Sequential hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed, the read command transmits the Read requested data to the host system continuing read-ahead without newly allocating the buffer for read.
Page 255 6.4 Read-ahead Cache 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data is started from the location where hit data is stored. For data that is a target of caching and remains before a full hit, the data is retained when execution of the command is completed.
Page 256 Operations 6.4.3.4 Partial hit In this situation, a part of read requested data including the top sector is stored in the data buffer. A transfer of the read requested data starts from the address where the data that is hit is stored until the top sector of the read requested data. Remaining part of insufficient data is read then.
Page 257: Write Cache
6.5 Write Cache 6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media. When Write Cache is permitted, the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer.
Page 258 Operations (3) Status report in the event of an error The status report concerning an error occurring during writing onto media is created when the next command is issued. Where the command reporting the error status is not executed, only the error status is reported. Only the status of an error that occurs during write processing is reported.
Page 259 6.5 Write Cache If Write Cache is enabled, there is a possibility that data transferred from the host with the Write Cache enable command is not completely written on disk media before the normal end interrupt is issued. If an unrecoverable error occurs while multiple commands that are targets of write caching are received, the host has difficulty determining which command caused the error.
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Page 261: Glossary
Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
Page 262 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Page 263 Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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Page 265: Acronyms And Abbreviations
Acronyms and Abbreviations ABRT Aborted command IDNF ID not found Automatic idle control IRQ14 Interrupt request 14 AMNF Address mark not found AT attachment American wire gage Light emitting diode Bad block detected Mega-byte BIOS Basic input-output system MB/S Mega-byte per seconds Micro processor unit CORR Corrected data...
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Page 267: Index
Index 1 drive connection ........2-3 caching operation........6-13 2 drives configuration ....... 2-4 CHECK POWER MODE....5-39, 6-9 2 drives connection ........2-4 CHECK POWER MODE command ..6-8 2MB buffer..........6-12 check sum ......5-51, 5-54, 5-55 circuit configuration ......4-3, 4-5 command block register ......
Page 268 Index data format of SMART summary EXECUTE DEVICE DIAGNOSTIC ..5-28 error log ..........5-53 execution example of READ data format version number..... 5-47 MULTIPLE command ......5-63 data register ..........5-8 execution timing of self-calibration...4-8 data transfer mode ........5-90 data, target of caching ......6-13 data-surface servo format ......
Page 269 Index multiword DMA data transfer timing..5-150 I/O register ..........5-7 IDENTIFY DEVICE....... 5-76 IDENTIFY DEVICE DMA ....5-77 normal DMA data transfer..... 5-136 IDLE..........5-37, 6-9 IDLE IMMEDIATE......5-34, 6-9 Information to be read by IDENTIFY off-line data collection capability .... 5-50 DEVICE command.....
Page 270 Index selective self-test feature flag ....5-57 selective self-test log data structure ..5-56 raw attribute value ........5-48 selective self-test pending time....5-57 READ BUFFER ........5-73 self-calibration ...........4-7 read circuit..........4-10 self-calibration content ......4-7 READ DMA..........5-69 self-diagnosis ..........1-3 READ DMA (EXT) ........ 6-12 self-test execution status ....5-49, 5-55 READ DMA EXT .........
Page 271 Index standby mode ..........6-8 ultra DMA feature set......5-137 start mode..........4-19 ultra DMA sender and recipient status ............5-54 timing requirement......5-154 status flag ..........5-48 ultra DMA termination with pull-up status register........... 5-11 or pull-down........5-148 status report in event of error ....6-20 unload feature ..........
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Page 273 List any errors or suggestions for improvement. Page Line Contents Please send this form to the address below. We will use your comments in planning future editions. Address: Fujitsu Learning Media Limited 37-10 Nishikamata 7-chome Oota-ku Tokyo 144-0051 JAPAN Fax: 81-3-3730-3702...
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Mhw2060at Mhw2040at

Fujitsu MHW2080AT Product Manual

CHAPTER 1 Device Overview

CHAPTER 2 Device Configuration

CHAPTER 3 Installation Conditions

CHAPTER 4 Theory of Device Operation

CHAPTER 5 Interface

CHAPTER 6 Operations

Glossary

Acronyms and Abbreviations

Index

Quick Links

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Summary of Contents for Fujitsu MHW2080AT