Fujitsu MHN2100AT - Mobile 10 GB Hard Drive Product Manual
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Fujitsu MHN2100AT - Mobile 10 GB Hard Drive Product Manual

Fujitsu MHN2100AT - Mobile 10 GB Hard Drive Product Manual

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C141-E120-02EN
MHN2300AT, MHN2200AT,
MHN2150AT, MHN2100AT
DISK DRIVES
PRODUCT MANUAL

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Summary of Contents for Fujitsu MHN2100AT - Mobile 10 GB Hard Drive

  • Page 1 C141-E120-02EN MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT DISK DRIVES PRODUCT MANUAL...
  • Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
  • Page 3 Revision History (1/1)
  • Page 4 This page is intentionally left blank.
  • Page 5 Preface This manual describes the MHN Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

  • Page 6: Operating Environment

    Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does...
  • Page 7 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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  • Page 9: Important Alert Items

    Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.
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  • Page 11: Manual Organization

    Manual Organization MHN2300AT, MHN2200AT, • Device Overview MHN2150AT, MHN2100AT • Device Configuration • Installation Conditions DISK DRIVES • Theory of Device Operation PRODUCT MANUAL • Interface (C141-E120) • Operations <This manual> MHN2300AT, MHN2200AT, • Maintenance and Diagnosis MHN2150AT, MHN2100AT • Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL (C141-E120)
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  • Page 13: Table Of Contents

    Contents CHAPTER 1 Device Overview................ 1-1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Specifications 1.2.1 Specifications summary 1.2.2 Model and product number Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate 1-10 Media Defects 1-10 1.10 Load/Unload Function 1-10...
  • Page 14 Contents CHAPTER 3 Installation Conditions ............. 3-1 Dimensions Mounting Cable Connections 3.3.1 Device connector 3.3.2 Cable connector specifications 3-10 3.3.3 Device connection 3-10 3.3.4 Power supply connector (CN1) 3-11 Jumper Settings 3-11 3.4.1 Location of setting jumpers 3-11 3.4.2 Factory default setting 3-12 3.4.3 Master drive-slave drive setting...
  • Page 15 Contents 4.6.2 Write circuit 4-10 4.6.3 Read circuit 4-13 4.6.4 Digital PLL circuit 4-14 Servo Control 4-15 4.7.1 Servo control circuit 4-15 4.7.2 Data-surface servo format 4-18 4.7.3 Servo frame format 4-20 4.7.4 Actuator motor control 4-21 4.7.5 Spindle motor control 4-22 CHAPTER 5 Interface ..................

  • Page 16: Chapter 6 Operations

    Contents 5.5.3.1 Initiating an Ultra DMA data in burst 5-100 5.5.3.2 The data in transfer 5-101 5.5.3.3 Pausing an Ultra DMA data in burst 5-101 5.5.3.4 Terminating an Ultra DMA data in burst 5-102 5.5.4 Ultra DMA data out commands 5-105 5.5.4.1 Initiating an Ultra DMA data out burst 5-105...
  • Page 17 Contents Power Save 6.2.1 Power save mode 6.2.2 Power commands Defect Management 6.3.1 Spare area 6.3.2 Alternating defective sectors Read-Ahead Cache 6-11 6.4.1 Data buffer configuration 6-12 6.4.2 Caching operation 6-12 6.4.3 Usage of read segment 6-14 6.4.3.1 Mis-hit (no hit) 6-14 6.4.3.2 Sequential read 6-15...
  • Page 18 Contents Illustrations Figures Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on Figure 2.1 Disk drive outerview Figure 2.2 Configuration of disk media heads Figure 2.3 1 drive system configuration Figure 2.4 2 drives configuration Figure 3.1 Dimensions Figure 3.2 Orientation...
  • Page 19 Contents Figure 5.2 Execution example of READ MULTIPLE command 5-19 Figure 5.3 Read Sector(s) command protocol 5-91 Figure 5.4 Protocol for command abort 5-92 Figure 5.5 WRITE SECTOR(S) command protocol 5-94 Figure 5.6 Protocol for the command execution without data transfer 5-95 Figure 5.7 Normal DMA data transfer...
  • Page 20 Contents Table 5.1 Signal assignment on the interface connector Table 5.2 I/O registers Table 5.3 Command code and parameters 5-14 Table 5.4 Information to be read by IDENTIFY DEVICE command 5-32 Table 5.5 Features register values and settable modes 5-41 Table 5.6 Diagnostic code 5-53...

  • Page 21: Device Overview

    CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects 1.10 Load/Unload Function Overview and features are described in this chapter, and specifications and power requirement are described. The MHN Series are 2.5-inch hard disk drives with built-in disk controllers. These disk drives use the AT-bus hard disk interface protocol and are compact and reliable.

  • Page 22: Features

    Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the MHN Series are described. (1) Compact The MHN2300AT, MHN2200AT, MHN2150AT and MHN2100AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch). (2) Large capacity The disk drive can record up to 15 GB (formatted) on one disk using the 16/17 MTR recording method and 15 recording zone technology.

  • Page 23: Interface

    1.1 Features 1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller, the disk drives (the MHN Series) can be connected to an ATA interface of a personal computer. (2) 2 MB data buffer The disk drives (the MHN Series) use a 2 MB data buffer to transfer data between the host and the disk media.

  • Page 24: Device Specifications

    Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHN Series). Table 1.1 Specifications (1/2) MHN2300AT MHN2200AT MHN2150AT MHN2100AT Format Capacity (*1) 30 GB 20 GB 15 GB 10 GB Number of Heads Number of Cylinders (User) 28,416 Number of Sectors (User)

  • Page 25: Model And Product Number

    1.3 Power Requirements Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Table 1.1 Specifications (2/2) Model Capacity No. of Cylinder No. of Heads No. of Sectors MHN2300AT 8.45 GB 16,383...

  • Page 26: Table 1.3 Current And Power Dissipation

    Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) MHN Series MHN Series Spin up (*1) 0.9 A 4.5 W Idle 150 mA 0.75 W...

  • Page 27: Environmental Specifications

    1.4 Environmental Specifications Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on (5) Power on/off sequence The voltage detector circuits (the MHN Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 28: Acoustic Noise

    Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification Sound Pressure • Idle mode (DRIVE READY) 24 dBA typical at 1 m Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.

  • Page 29: Reliability

    1.7 Reliability 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20% or less of power-on time Power on/off 1/day or more needed. Environment 5 to 55°C/8 to 90% But humidity bulb temperature 29°C or less MTBF is defined as follows:...

  • Page 30: Error Rate

    Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...
  • Page 31 1.7 Reliability Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.
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  • Page 33: Chapter 2 Device Configuration

    CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E120-02EN...

  • Page 34: Device Configuration

    Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. MHN Series Figure 2.1 Disk drive outerview (1) Disk...

  • Page 35: Figure 2.2 Configuration Of Disk Media Heads

    2.1 Device Configuration Head Head Head MHN2300AT MHN2200AT MHN2150AT (Either of head 0 or MHN2100AT head 3 is mounted.) Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat.

  • Page 36: System Configuration

    Device Configuration 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 transfer at 100 MB/s.
  • Page 37 2.2 System Configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-5 interface. At high speed data transfer (PIO mode 4 or DMA mode 2 U-DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
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  • Page 39: Chapter 3 Installation Conditions

    CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.

  • Page 40: Dimensions

    Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. 0.25 Figure 3.1 Dimensions C141-E120-02EN...

  • Page 41: Mounting

    3.2 Mounting 3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (d) Vertical –2 (c) Vertical –1 gravity (e) Vertical –3 (f) Vertical –4 Figure 3.2 Orientation C141-E120-02EN...

  • Page 42: Figure 3.3 Mounting Frame Structure

    Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N·m(5kgf·cm).

  • Page 43: Figure 3.4 Location Of Breather

    3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around 3 to block.

  • Page 44: Figure 3.5 Surface Temperature Measurement Points

    Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C.

  • Page 45: Figure 3.6 Service Area

    3.2 Mounting (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.

  • Page 46: Figure 3.7 Handling Cautions

    Installation Conditions General notes ESD mat Wrist strap Shock absorbing mat Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically Do not drop.

  • Page 47: Cable Connections

    3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.8 Connector locations C141-E120-02EN...

  • Page 48: Cable Connector Specifications

    Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 BERG supply cable (44-pin type) (44-pin type) IMPORTANT For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.

  • Page 49: Power Supply Connector (Cn1)

    3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions.

  • Page 50: Factory Default Setting

    Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Short Open...

  • Page 51: Csel Setting

    3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables.

  • Page 52: Figure 3.16 Example (2) Of Cable Select

    Installation Conditions drive drive Figure 3.16 Example (2) of Cable Select 3-14 C141-E120-02EN...

  • Page 53: Theory Of Device Operation

    CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

  • Page 54: Outline

    Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

  • Page 55: Spindle

    4.2 Subassemblies Head Head Head MHN2300AT MHN2200AT MHN2150AT (Either of head 0 or MHN2100AT head 3 is mounted.) Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm 1%.

  • Page 56: Circuit Configuration

    Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

  • Page 57: Figure 4.2 Power Supply Configuration

    4.3 Circuit Configuration 5.0V S-DRAM HDIC F-ROM - 3.0V 3.3V 2.5V & Figure 4.2 Power Supply Configuration C141-E120-02EN...

  • Page 58: Figure 4.3 Circuit Configuration

    Theory of Device Operation Figure 4.3 Circuit Configuration C141-E120-02EN...

  • Page 59: Power-On Sequence

    4.3 Circuit Configuration 4.4 Power-on Sequence Figure 4.4 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

  • Page 60: Self-Calibration

    Theory of Device Operation Power-on Start Self-diagnosis 1 - MPU bus test - Internal register write/read test - Work RAM write/read test The spindle motor starts. Self-diagnosis 2 - Data buffer write/read Initial on-track and read test out of system information Confirming spindle motor Execute self-calibration speed...

  • Page 61: Execution Timing Of Self-Calibration

    4.5 Self-calibration The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varying by the cylinder, the disk is divided into 23 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.

  • Page 62: Command Processing During Self-Calibration

    Theory of Device Operation 4.5.3 Command processing during self-calibration If the disk drive receives a command execution request from the host while executing self-calibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and restarts calibration.

  • Page 63: Table 4.1 Write Precompensation Algorithm

    4.6 Read/write Circuit Table 4.1 Write precompensation algorithm Bits Compensation 111001 –7 111010 –6 111111 –1 000000 000001 010000 100000 C141-E120-02EN 4-11...

  • Page 64: Figure 4.5 Read/Write Circuit Block Diagram

    Theory of Device Operation HDIC WDX/WDY RDX/RDY Serial I/O Write Amplifier PreCompen- sation Registers Digital Programmable Filter Flash Digitizer ServoPulse MEEPR Detector Viterbi Detect 16/17 ENDEC Position A/B/C/D (to reg) WTGATE REFCLK RDGATE DATA RWCLK SRV_CLK SRV_OUT[1:0] [7:0] Figure 4.5 Read/write circuit block diagram 4-12 C141-E120-02EN...

  • Page 65: Read Circuit

    4.6 Read/write Circuit 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 66: Digital Pll Circuit

    Theory of Device Operation (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosine- equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit.

  • Page 67: Servo Control

    4.7 Servo Control 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
  • Page 68 Theory of Device Operation The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).
  • Page 69 4.7 Servo Control (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.9 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head.

  • Page 70: Data-Surface Servo Format

    Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.

  • Page 71: Figure 4.8 Physical Sector Servo Configuration On Disk Surface

    4.7 Servo Control Servo frame (120 servo frames per revolution) Data area expand CYLn CYLn – 1 (n: even number) CYLn + 1 Diameter direction W/R Recovery W/R Recovery W/R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code Erase Servo A...

  • Page 72: Servo Frame Format

    Theory of Device Operation 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks;...

  • Page 73: Actuator Motor Control

    4.7 Servo Control (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.

  • Page 74: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
  • Page 75 4.7 Servo Control d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal.
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  • Page 77: Chapter 5 Interface

    CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E120-02EN...

  • Page 78: Physical Interface

    Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DATA 0-15: DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...

  • Page 79: Signal Assignment On The Connector

    5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL unused ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...
  • Page 80 Interface [signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...
  • Page 81 5.1 Physical Interface [signal] [I/O] [Description] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

  • Page 82: Logical Interface

    Interface [signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.

  • Page 83: I/O Registers

    5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

  • Page 84: Command Block Registers

    Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
  • Page 85 5.2 Logical Interface [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration.
  • Page 86 Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8.
  • Page 87 5.2 Logical Interface (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 88 Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

  • Page 89: Host Commands

    5.3 Host Commands 5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
  • Page 90 Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.
  • Page 91 5.3 Host Commands Table 5.3 Command code and parameters (2 of 2) Command code (Bit) Parameters used Command name FR SC SN CY DH IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD...

  • Page 92: Command Descriptions

    Interface Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored. The command is addressed to the master device, but both the master device and the slave device execute it.
  • Page 93 5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note:...
  • Page 94 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) (R: Retry) At command completion (I/O registers contents to be read)
  • Page 95 5.3 Host Commands final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”). If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.
  • Page 96 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (*1) (SC) (ER)
  • Page 97 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 98 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)
  • Page 99 5.3 Host Commands If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.
  • Page 100 Interface (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
  • Page 101 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 102 Interface A host system can select the following transfer mode using the SET FEATURES command. Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No.
  • Page 103 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 104 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’...

  • Page 105: Specifications

    5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Head No. / LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)

  • Page 106: C141-E120-02En

    Interface At command issuance (I/O registers setting contents) (CM) (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (ER)
  • Page 107 5.3 Host Commands (13) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 108 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3) Word Value Description...
  • Page 109 5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3) Word Value Description 23-26 – Firmware revision (ASCII code, 8 characters, left) 27-46 Set by a device Model name (ASCII code, 40 characters, left) X’8010’...
  • Page 110 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 8) Word Value Description Valid of command sets/function *13 Valid of command sets/function *14 Default of command sets/function *15 X’xx3F’ Ultra DMA transfer mode *16 Set by a device Security Erase Unit execution time (Unit: 2 min.) X’0000’...
  • Page 111 5.3 Host Commands Bit 13: Standby timer value. Factory default is '0.' ATA spec is '1.' Bit 12: Reserved Bit 11: 1 = Supported Bit 10: 0 = Disable inhibition Bit 7-0: Undefined Bit 8: 1 = LBA Supported Bit 9: 1 = DMA Supported *4 Word 51: PIO data transfer mode Bit 15-8:...
  • Page 112 Interface Bit 1: 1 = Mode 4 Bit 0: 1 = Mode 3 *9 WORD 80 Bit 15-7: Reserved Bit 6: 1 = ATA/ATAPI-6 supported Bit 5: 1 = ATA/ATAPI-5 supported Bit 4: 1 = ATA/ATAPI-4 supported Bit 3: 1 = ATA-3 supported Bit 2: 1 = ATA-2 supported Bit 1-0:...
  • Page 113 5.3 Host Commands Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10: '1' = 48 bit LBA feature set. Bit 9: '1' = Automatic Acoustic Management feature set. Bit 8: '1' = Supports the SET MAX Security extending command.
  • Page 114 Interface Bit 5: '1' = Enables the write cache function. Bit 4: '1' = Enables the P PACKET command set. Bit 3: '1' = Enables the Power Management function. Bit 2: '1' = Enables the Removable Media function. Bit 1: '1' = Enables the Security Mode function.
  • Page 115 5.3 Host Commands *17 WORD 93 Bits 15-14: Reserved Bit 13: '1' = CBLID- is a level higher than V '0' = CBLID- is a level lower than V Bits 12-8: In the case of Device 1 (slave drive), a valid value is set. Bit 12: Reserved Bit 11:...
  • Page 116 Interface Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2: '1' = Security locked Bit 1: '1' = Security enabled Bit 0: '1' = Security supported (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed.
  • Page 117 5.3 Host Commands Table 5.5 Features register values and settable modes Features Drive operation mode Register X’02’ Enables the write cache function. X’03’ Set the data transfer mode. *1 X’05’ Enables the advanced power management function. *2 X’42’ Enables the Acoustic management function. *3 X’55’...
  • Page 118 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or *1~3 (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information *1) Data Transfer Mode The host sets X’03’...
  • Page 119 5.3 Host Commands Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) 01000 101 (X’45’: Mode 5)
  • Page 120 Interface then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets. AAM Level Sector Count register Standard Seek C0h-FEh, 00h Slow Seek 80h-BFh Reserved 01h-7Fh, FFh Standard Seek : Maximum performance Slow Seek : Minimum acoustic emanation...
  • Page 121 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) After power-on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode. At command completion (I/O registers contents to be read) (ST) Status information (DH)
  • Page 122 Interface SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.
  • Page 123 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information SET MAX SET PASSWORD (FR = 01h) This command requests a transfer of 1 sector of data from the host, and defines the contents of SET MAX password.
  • Page 124 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Password information Words Contents Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
  • Page 125 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.
  • Page 126 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX FREEZE LOCK (FR=04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
  • Page 127 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (17) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.
  • Page 128 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device.
  • Page 129 5.3 Host Commands Table 5.6 Diagnostic code Code Result of diagnostic X’01’ No error detected. X’03’ Data buffer compare error X’05’ ROM sum check error X’8x’ Failure of device 1 attention: The device responds to this command with the result of power-on diagnostic test.
  • Page 130 Interface (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
  • Page 131 5.3 Host Commands (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
  • Page 132 Interface (21) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
  • Page 133 5.3 Host Commands (22) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data.
  • Page 134 Interface (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode.
  • Page 135 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 136 Interface (25) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode.
  • Page 137 5.3 Host Commands (26) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence. At command issuance (I/O registers setting contents) (CM) X’94’...
  • Page 138 Interface (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.
  • Page 139 5.3 Host Commands (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value.
  • Page 140 Interface (29) SMART (X’B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command.
  • Page 141 5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 142 Interface Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.

  • Page 143: At Command Issuance (I/O Registers Setting Contents)

    5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.

  • Page 144: 1F6 (Dh)

    Interface At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h/2Ch) (CL) Key-failure prediction status (4Fh/F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown the following table 5.8.
  • Page 145 5.3 Host Commands Table 5.8 Format of device attribute value data Byte Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far 07 to 0C Raw attribute value Reserved 0E to 169 Attribute 2 to (The format of each attribute value is the same...
  • Page 146 Interface Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same.
  • Page 147 5.3 Host Commands Meaning If this bit 1, it indicates the attribute that represents an error rate. If this bit 1, it indicates the attribute that represents the number of occurrences. If this bit 1, it indicates the attribute that can be collected/saved even if the drive fault prediction function is disabled.
  • Page 148 Interface Self-test Meaning execution status Self-test has been completed normally or has not been executed. Self-test has been stopped by the host computer. Self-test has been suspended by hard or soft reset. Self-test has been aborted by a fatal error. Self-test has been completed abnormally by an unknown meaning.
  • Page 149 5.3 Host Commands Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.
  • Page 150 Interface Table 5.11 SMART error log data format Byte Item Error log version number Error log index Error log 1 Command Data 1 Device Control register Features register Sector Count register Sector Number register Cylinder Low register Cylinder High register Device/Head register Command register 0A to 0D...
  • Page 151 5.3 Host Commands Error log index Indicates the latest error log number. If an error has not occurred, 00 is displayed. Error log 1 to 5 When an error occurs, the error log index value is incremented and information at the time the error occurred is recorded in the error log area specified by this value.
  • Page 152 Interface Table 5.12 SMART self test log data format Byte Item 00, 01 Self test log data format version number Self test log 1 Self test mode (SN Register Value) Self test execution status 04, 05 Total power on time until the self test is completed.
  • Page 153 5.3 Host Commands Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error. (The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE.) Table 5.13 Contents of security password Word Contents Control word Bit 0: Identifier 0 = Compares the user passwords.
  • Page 154 Interface (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
  • Page 155 5.3 Host Commands Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password. If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.
  • Page 156 Interface SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off, or when hardware is reseted. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged. Issuing this command during LOCKED MODE returns the Aborted Command error.
  • Page 157 5.3 Host Commands (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.13 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
  • Page 158 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.12 to the device. Operation of the device varies as follows depending on whether the host specifies the master password.
  • Page 159 5.3 Host Commands UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted Command error until the device is turned off and then on, or until a hardware reset is executed. Issuing this command with LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter.
  • Page 160 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (37) DEVICE CONFIGURATION (B1) Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register.
  • Page 161 5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) C0h/C1h/C2h/C3h At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information DEVICE CONFIGURATION RESTORE (FR=C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a...
  • Page 162 Interface If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power-up, an aborted error is posted. DEVICE CONFIGURATION IDENTIFY (FR=C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5.16. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting.
  • Page 163 5.3 Host Commands Table 5.16 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content X'0001' Data structure revision X'0007' Multiword DMA modes supported Bit 15-3: Reserved Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0: 1 = Multiword DMA mode 0 is supported X'003F'...

  • Page 164: Error Posting

    Interface 5.3.3 Error posting Table 5.15 lists the defined errors that are valid for each command. Table 5.17 Command code and parameters (1 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) ICRC INDF ABRT TK0NF DRDY READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE...
  • Page 165 5.3 Host Commands Table 5.17 Command code and parameters (2 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) ICRC INDF ABRT TK0NF DRDY SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK FLUSH CACHE...

  • Page 166: Command Protocol

    Interface 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1.
  • Page 167 5.4 Command Protocol words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register...

  • Page 168: Pio Data Transferring Commands From Host To Device

    Interface device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.
  • Page 169 5.4 Command Protocol The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers.

  • Page 170: Write Sector(S) Command Protocol

    Interface Figure 5.5 WRITE SECTOR(S) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
  • Page 171 5.4 Command Protocol SEEK READY VERIFY SECTOR(S) EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS READ NATIVE MAX ADDRESS IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE/DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS...

  • Page 172: Other Commands

    Interface 5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
  • Page 173 5.4 Command Protocol The interrupt processing for the DMA transfer differs the following point. The interrupt processing for the DMA transfer differs the following point. a) The host writes any parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head register. b) The host initializes the DMA channel c) The host writes a command code in the Command register.
  • Page 174 Interface Figure 5.7 Normal DMA data transfer 5-98 C141-E120-02EN...

  • Page 175: Ultra Dma Feature Set

    5.5 Ultra DMA Feature Set 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host.

  • Page 176: Phases Of Operation

    Interface device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.
  • Page 177 5.5 Ultra DMA Feature Set 8) The device may assert DSTROBE t after the host has asserted DMACK-. ZIORDY Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.
  • Page 178 Interface NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t before asserting STOP.
  • Page 179 5.5 Ultra DMA Feature Set 6) The host shall drive DD (15:0) no sooner than t after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP.
  • Page 180 Interface after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t timing for the device. 5) The host shall assert STOP no sooner than t after negating HDMARDY-.

  • Page 181: Ultra Dma Data Out Commands

    5.5 Ultra DMA Feature Set 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
  • Page 182 Interface Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t for the selected Ultra DMA mode. 3) The host shall not change the state of DD (15:0) until at least t after generating an HSTROBE edge to latch the data.
  • Page 183 5.5 Ultra DMA Feature Set 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
  • Page 184 Interface b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

  • Page 185: Ultra Dma Crc Rules

    5.5 Ultra DMA Feature Set 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at...

  • Page 186: Series Termination Required For Ultra Dma

    Interface The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.

  • Page 187: Pio Data Transfer

    5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Min. Max. Unit Cycle time —...
  • Page 188 Interface 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. DMARQ DMACK- DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 Symbol Timing parameter Min. Max. Unit Cycle time — Delay time from DMACK assertion to DMARQ negation —...

  • Page 189: Ultra Dma Data Transfer

    5.6 Timing 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.20 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

  • Page 190: Ultra Dma Data Burst Timing Requirements

    Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT...
  • Page 191 5.6 Timing Table 5.18 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Limited interlock time (*1) Interlock time with minimum (*1) Unlimited interlock time (*1)
  • Page 192 Interface Table 5.19 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 Recipient IC data setup time (from DSIC...
  • Page 193 5.6 Timing 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC 2CYC DSTROBE at device DVHIC DVSIC DVHIC DVSIC DVHIC DD(15:0) at device DSTROBE at host DHIC DHIC DSIC DHIC...
  • Page 194 Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
  • Page 195 5.6 Timing 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are...
  • Page 196 Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
  • Page 197 5.6 Timing 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DZFS DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
  • Page 198 Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC HSTROBE 2CYC at host DVHIC DVHIC DVHIC DVSIC DVSIC DD(15:0) at host HSTROBE at device DHIC DSIC DHIC DSIC DHIC...
  • Page 199 5.6 Timing 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.
  • Page 200 Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
  • Page 201 5.6 Timing 5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...

  • Page 202: Power-On And Reset

    Interface 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device]...
  • Page 203 CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Power Save 6.3 Defect Management 6.4 Read-Ahead Cache 6.5 Write Cache C141-E120-02EN...

  • Page 204: Device Response To The Reset

    Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).

  • Page 205: Response To Hardware Reset

    6.1 Device Response to the Reset Power on Master device Power On Reset- Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to If presence of a slave device is 450 ms. confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On Reset- BSY bit...
  • Page 206 Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 400 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. Reset- Master device Status Reg.

  • Page 207: Response To Software Reset

    6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 208: Response To Diagnostic Command

    Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.

  • Page 209: Power Save

    6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are four types of power consumption state of the device including active mode where all circuits are active.

  • Page 210: Power Commands

    Operations takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately. The drive enters the standby mode under the following conditions: A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode.

  • Page 211: Defect Management

    6.3 Defect Management 6.3 Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment. All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6.1.
  • Page 212 Operations (unused) Note: If an access request to logical sector 4 is specified, the device accesses physical sector 5 instead of sector 4. Figure 6.5 Sector slip processing (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence.

  • Page 213: Read-Ahead Cache

    6.4 Read-Ahead Cache Index Sector (Physical) Cylinder 0 Defective sector Head 0 (unused) Sector (Logical) Alternate cylinder Already assigned Head 0 Defective sector is assigned to unassigned sector. Notes: 1) 4 alternate cylinders are provided for each head in zone 14 (inner side).

  • Page 214: Data Buffer Configuration

    Operations When the next command requests to read the read-ahead data, the data can be transferred from the data buffer without accessing the disk medium. The host can thus access data at higher speed. 6.4.1 Data buffer configuration The drive has a 2 MB data buffer. The buffer is used by divided into three parts; for read/write commands, and for MPU work (see Figure 6.9).
  • Page 215 6.4 Read-Ahead Cache 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation. 2) Data transferred to the host system once by requesting with the command that are object of caching operation (except for the cache invalid data by some reasons).

  • Page 216: Usage Of Read Segment

    Operations 6) The device enters the sleep mode. 7) Under the state that the write data is kept in the data buffer for write command as a caching data, new write command is issued. (write data kept until now are invalidated) 6.4.3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases.
  • Page 217 6.4 Read-Ahead Cache 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation. (stopped) Empty area Read-requested data (stopped) 4) Following shows the cache enabled data for next read command. Empty area Cache enabled data Start LBA...
  • Page 218 Operations 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data. Requested data Mis-hit data Empty area 3) After completion of the reading and transferring the requested data to the host system, the disk drive performs the read-ahead operation continuously.
  • Page 219 6.4 Read-Ahead Cache 1) In the case that the contents of buffer is as follows at receiving a read command; HAP (Continued from the previous read request data) Read-ahead data Hit data Last LBA Start LBA 2) The disk drive starts the read-ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data.
  • Page 220 Operations 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA Non-sequential command immediately after sequential command When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received.
  • Page 221 6.4 Read-Ahead Cache 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.4.3.4 Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.

  • Page 222: Write Cache

    Operations 3) The cache data for next read command is as follows. Cache data Start LBA Last LBA 6.5 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed.
  • Page 223 6.5 Write Cache The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed. If an error occurs during the write operation, the device retries the processing.
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  • Page 225 Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
  • Page 226 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
  • Page 227 Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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  • Page 229: Acronyms And Abbreviations

    Acronyms and Abbreviations Hard disk drive ABRT Aborted command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...
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  • Page 231 List any errors or suggestions for improvement. Page Line Contents Please send this form to the address below. We will use your comments in planning future editions. Address: Fujitsu Learning Media Limited 22-7 Minami-Ooi 6-Chome Shinagawa-Ku Tokyo 140-0013 JAPAN Fax: 81-3-5762-8073...
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  • Page 233 MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT C141-E120-02EN DISK DRIVES PRODUCT MANUAL MHN2300AT, MHN2200AT, MHN2150AT, MHN2100AT C141-E120-02EN DISK DRIVES PRODUCT MANUAL...
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