Page 1 C141-E202-01EN MHU2100AT DISK DRIVE PRODUCT MANUAL...
Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Page 3: Revision History
Revision History (1/1) Revised section (*1) Edition Date Details (Added/Deleted/Altered) 2004-01-20 *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E202-01EN...
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Page 5 Preface This manual describes MHU2100AT model of the MHU Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.
Page 6: Operating Environment
Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does...
Page 7 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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Page 9: Important Alert Items
Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.
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Page 11: Manual Organization
Manual Organization MHU2100AT • Device Overview • Device Configuration DISK DRIVE • Installation Conditions PRODUCT MANUAL • Theory of Device Operation (C141-E202) • Interface • Operations <This manual> MHU2100AT • Maintenance and Diagnosis • Removal and Replacement Procedure DISK DRIVE...
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Page 13: Table Of Contents
Contents CHAPTER 1 Device Overview................ 1-1 1.1 Features ......................1-2 1.1.1 Functions and performance ..............1-2 1.1.2 Adaptability .....................1-2 1.1.3 Interface....................1-3 1.2 Device Specifications ..................1-4 1.2.1 Specifications summary ................1-4 1.2.2 Model and product number ..............1-5 1.3 Power Requirements...................1-6 1.4 Environmental Specifications ................1-8 1.5 Acoustic Noise ....................1-9 1.6 Shock and Vibration...................1-9 1.7 Reliability ......................1-10...
Page 14 Contents CHAPTER 3 Installation Conditions ............. 3-1 3.1 Dimensions ......................3-2 3.2 Mounting......................3-3 3.3 Cable Connections ..................... 3-9 3.3.1 Device connector ..................3-9 3.3.2 Cable connector specifications ............. 3-10 3.3.3 Device connection ................3-10 3.3.4 Power supply connector (CN1) ............3-11 3.4 Jumper Settings....................
Page 15 Contents 4.6.2 Write circuit.....................4-9 4.6.3 Read circuit....................4-10 4.6.4 Digital PLL circuit.................4-11 4.7 Servo Control ....................4-12 4.7.1 Servo control circuit ................4-12 4.7.2 Data-surface servo format ..............4-15 4.7.3 Servo frame format................4-17 4.7.4 Actuator motor control ................4-18 4.7.5 Spindle motor control................4-19 CHAPTER 5 Interface ..................
Page 16 Contents (13) IDLE IMMEDIATE (X’95’ or X’E1’) .........5-36 (14) STANDBY (X’96’ or X’E2’) ............5-37 (15) IDLE (X’97’ or X’E3’) ..............5-38 (16) CHECK POWER MODE (X’98’ or X’E5’) .........5-40 (17) SLEEP (X’99’ or X’E6’) ..............5-41 (18) SMART (X’B0) ................5-42 (19) DEVICE CONFIGURATION (X'B1')..........5-59 (20) READ MULTIPLE (X’C4’) ............5-63 (21) WRITE MULTIPLE (X’C5’) ............5-65 (22) SET MULTIPLE MODE (X’C6’) ..........5-67...
Page 17 Contents (46) SET MAX ADDRESS EXT (X’37’): Option (customizing)................5-117 (47) WRITE MULTIPLE EXT (X’39’): Option (customizing)..5-119 (48) WRITE LOG EXT (X’3F’) [Optional command (Customize)] ................5-120 (49) READ VERIFY SECTOR (S) EXT (X’42): Option (customizing)................5-122 (50) FLUSH CACHE EXT (X’EA’): Option (customizing)..... 5-123 5.3.3 Error posting..................5-124 5.4 Command Protocol..................5-126 5.4.1 PIO Data transferring commands from device to host......5-126...
Page 18 Contents 5.6.3.1 Initiating an Ultra DMA data in burst ........5-148 5.6.3.2 Ultra DMA data burst timing requirements ......5-149 5.6.3.3 Sustained Ultra DMA data in burst ......... 5-152 5.6.3.4 Host pausing an Ultra DMA data in burst....... 5-153 5.6.3.5 Device terminating an Ultra DMA data in burst ..... 5-154 5.6.3.6 Host terminating an Ultra DMA data in burst......
Page 19 Contents 6.4.3.1 Miss-hit ..................6-15 6.4.3.2 Sequential Hit................6-16 6.4.3.3 Full hit ..................6-17 6.4.3.4 Partial hit ..................6-18 6.5 Write Cache......................6-19 6.5.1 Cache operation..................6-19 Glossary ......................GL-1 Acronyms and Abbreviations.................AB-1 Index ......................... IN-1 C141-E202-01EN...
Page 20 Contents Illustrations Figures Figure 1.1 Negative voltage at +5 V when power is turned off ......1-6 Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on.................... 1-8 Figure 2.1 Disk drive outer view ................ 2-2 Figure 2.2 1 drive system configuration.............
Page 21 Contents Figure 5.2 Execution example of READ MULTIPLE command .....5-63 Figure 5.3 Read Sector(s) command protocol..........5-127 Figure 5.4 Protocol for command abort ............5-128 Figure 5.5 WRITE SECTOR(S) command protocol........5-130 Figure 5.6 Protocol for the command execution without data transfer ...................5-132 Figure 5.7 Normal DMA data transfer ............5-133 Figure 5.8...
Page 22 Contents Tables Table 1.1 Specifications ................... 1-4 Table 1.2 Examples of model names and product numbers......1-5 Table 1.3 Current and power dissipation............1-7 Table 1.4 Environmental specifications ............1-8 Table 1.5 Acoustic noise specification.............. 1-9 Table 1.6 Shock and vibration specification ............. 1-9 Table 1.7 Advanced Power Management............
Page 23 Contents Table 5.25 Relationship between combination of Identifier and Security level, and operation of the lock function ......5-92 Table 5.26 Contents of security password ............5-100 Table 5.27 Command code and parameters ............5-124 Table 5.28 Recommended series termination for Ultra DMA......5-145 Table 5.29 Ultra DMA data burst timing requirements ........5-149 Table 5.30 Ultra DMA sender and recipient timing requirements ....5-151 C141-E202-01EN...
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Page 25: Chapter 1 Device Overview
CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management Overview and features are described in this chapter, and specifications and power requirement are described.
Page 26: Features
The disk drive can record up to 50 GB (formatted) on one disk using the RLL recording method and 30 recording zone technology. The disk drive has a formatted capacity of 100 GB (MHU2100AT). (3) High-speed Transfer rate The disk drive (the MHU Series) has an internal data rate up to 41.3 MB/s. The disk drive supports an external data rate up to 100 MB/s (U-DMA mode 5).
Page 27: Interface
1.1 Features 1.1.3 Interface (1) Connection to ATA interface The disk drive has built-in controllers compatible with the ATA interface. (2) Data buffer The disk drive use a 8MB data buffer to transfer data between the host and the disk media. In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.
Page 28: Device Specifications
Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives. Table 1.1 Specifications (1 of 2) MHU2100AT Format Capacity (*1) 100 GB Number of Sectors (User) 195,371,568 sector Bytes per Sector 512 bytes Rotational Speed 4,200 rpm ±...
Page 29: Model And Product Number
Model Capacity No. of Cylinder No. of Heads No. of Sectors MHU2100AT 8.45 GB 16,383 1.2.2 Model and product number Table 1.2 lists the model names and product numbers of the disk drive. The model name does not necessarily correspond to the product number as listed in Table 1.2 since some models have been customized and have specifications...
Page 30: Power Requirements
Device Overview 1.3 Power Requirements (1) Input Voltage • + 5 V ± 5 % (2) Ripple +5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz (3) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned off and, a thing with no ringing.
Page 31: Table 1.3 Current And Power Dissipation
1.3 Power Requirements (4) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) Spin up (*1) 0.9 A 4.5 W Idle 130 mA 0.65 W R/W (on track) (*2) Read 400 mA / Write 420mA...
Page 32: Environmental Specifications
Device Overview (5) Current fluctuation (Typ.) at +5 V when power is turned on Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on (6) Power on/off sequence The voltage detector circuits monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal.
Page 33: Acoustic Noise
1.5 Acoustic Noise 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification (typical) • Idle mode (DRIVE READY) Sound Power 2.4B Sound Pressure (at 0.3m) 25.0dB Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.
Page 34: Reliability
Device Overview 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20 % or less of power-on time Environment 5 to 55 °C/8 to 90 % But humidity bulb temperature 29 °C or less MTBF is defined as follows: Total operation time in all fields...
Page 35: Error Rate
1.8 Error Rate 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...
Page 36: Advanced Power Management
Device Overview Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.
Page 37: Table 1.7 Advanced Power Management
1.11 Advanced Power Management Standby: The spindle motor stops. In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle." Table 1.7 Advanced Power Management Active Idle Low Power Idle Standby APM Mode (VCM Lock) (Unload)
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Page 39: Chapter 2 Device Configuration
CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E202-01EN...
Page 40: Device Configuration
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. Figure 2.1 Disk drive outer view (1) Disk The outer diameter of the disk is 65 mm.
Page 41: System Configuration
44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s). 2.2.2 1 drive connection MHC2032AT MHU2100AT MHC2040AT Figure 2.2 1 drive system configuration C141-E202-01EN...
Page 42: Drives Connection
Device Configuration 2.2.3 2 drives connection MHC2032AT MHU2100AT (Host adaptor) MHC2040AT MHC2032AT MHU2100AT MHC2040AT Note: When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed. Figure 2.3 2 drives configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver.
Page 43: Chapter 3 Installation Conditions
CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.
Page 44: Dimensions
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions C141-E202-01EN...
Page 45: Mounting
3.2 Mounting 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (c) Vertical –1 (d) Vertical –2 gravity (f) Vertical –4...
Page 46: Figure 3.3 Mounting Frame Structure
Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N•m (5kgf•cm).
Page 47: Figure 3.4 Location Of Breather
3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around φ...
Page 48: Figure 3.5 Surface Temperature Measurement Points
Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 °C.
Page 49: Figure 3.6 Service Area
3.2 Mounting (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.
Page 50: Figure 3.7 Handling Cautions
Installation Conditions General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically Do not drop.
Page 51: Cable Connections
3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.8 Connector locations C141-E202-01EN...
Page 52: Cable Connector Specifications
Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 supply cable (44-pin type) (44-pin type) IMPORTANT For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.
Page 53: Power Supply Connector (Cn1)
3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions.
Page 54: Factory Default Setting
Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Short Open...
Page 55: Csel Setting
3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables.
Page 56: Power Up In Standby Setting
Installation Conditions drive drive Figure 3.16 Example (2) of Cable Select 3.4.5 Power Up in Standby setting When pin C is grounded, the drive does not spin up at power on. 3-14 C141-E202-01EN...
Page 57: Chapter 4 Theory Of Device Operation
CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Page 58: Outline
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).
Page 59: Air Filter
4.3 Circuit Configuration 4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.
Page 60: Figure 4.1 Power Supply Configuration
Theory of Device Operation (4) Controller circuit Major functions are listed below. • ATA interface control and data transfer control • Data buffer management • Sector format control • Defect management • ECC control • Error recovery and self-diagnosis Figure 4.1 Power Supply Configuration C141-E202-01EN...
Page 61: Figure 4.2 Circuit Configuration
4.3 Circuit Configuration ATA Interface Console MCU & HDC & RDC Data Buffer (88i5531; Marvell) SDRAM Flash ROM FROM Shock TLS2255 Sensor Resonator 20MHz SP Motor Thermistor R/W Pre-Amp TLS26B624 HEAD Media Figure 4.2 Circuit Configuration C141-E202-01EN...
Page 62: Power-On Sequence
Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
Page 63: Self-Calibration
4.5 Self-calibration 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.
Page 64: Execution Timing Of Self-Calibration
Theory of Device Operation 4.5.2 Execution timing of self-calibration Self-calibration is performed once when power is turned on. After that, the disk drive does not perform self-calibration until it detects an error. That is, self-calibration is performed each time one of the following events occur: •...
Page 65: Read/Write Circuit
4.6 Read/write Circuit 4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) PreAMP equips a read preamplifier and a write current switch, that sets the bias current to the MR device and the current in writing.
Page 66: Read Circuit
Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
Page 67: Digital Pll Circuit
4.6 Read/write Circuit (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.
Page 68: Servo Control
Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
Page 69: Index
4.7 Servo Control (1) Microprocessor unit (MPU) The MPU executes startup of the spindle motor, movement to the reference cylinder, seek to the specified cylinder, and calibration operations. Main internal operation of the MPU are shown below. The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied.
Page 70 Theory of Device Operation (5) Spindle motor control circuit The spindle motor control circuit controls the sensor-less spindle motor. A spindle driver IC with a built-in PLL(FLL) circuit that is on a hardware unit controls the sensor-less spindle motor. (6) Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.
Page 71: Data-Surface Servo Format
4.7 Servo Control 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.
Page 72: Figure 4.7 Physical Sector Servo Configuration On Disk Surface
Theory of Device Operation Servo frame (160 servo frames per revolution) Data area expand CYLn CYLn – 1 (n: even number) CYLn + 1 Diameter direction W/R Recovery W/R Recovery W/R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code Erase...
Page 73: Servo Frame Format
4.7 Servo Control 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks;...
Page 74: Actuator Motor Control
Theory of Device Operation 4.7.4 Actuator motor control The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.
Page 75: Spindle Motor Control
(called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
Page 76 Theory of Device Operation pump for 0.714 ms × k (k: constant value). This makes the flowed current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,200 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution.
Page 77: Chapter 5 Interface
CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E202-01EN...
Page 78: Physical Interface
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DATA 0-15: DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...
Page 79: Signal Assignment On The Connector
5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL PUS- ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...
Page 80 Interface [signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...
Page 81 5.1 Physical Interface [signal] [I/O] [Description] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.
Page 82: Logical Interface
Interface [signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.
Page 83: I/O Registers
5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.
Page 84: Command Block Registers
Interface Device/Head, Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively. If the LBA mode is specified with 48-bit address information, the Cylinder High, Cylinder Low, Sector Number registers are set twice.
Page 85 5.2 Logical Interface - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred. [Diagnostic code] X’01’: No Error Detected.
Page 86 Interface (5) Sector Number register (X’1F3’) The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command. Under the LBA mode, this register indicates LBA bits 7 to 0.
Page 87 5.2 Logical Interface (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.). Bit 7 Bit 6 Bit 5...
Page 88 Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers.
Page 89: Control Block Registers
5.2 Logical Interface (10) Command register (X’1F7’) The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately. Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written.
Page 90: Command Code And Parameters
Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRST nIEN - Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command.
Page 91: Recalibrate (X'10' To X'1F')
5.3 Host Commands Table 5.3 Command code and parameters (1 of 2) PARAMETER USED COMMAND CODE（Bit） COMMAND NAME FR SC SN CY DH RECALIBRATE READ SECTOR(S) READ LONG WRITE SECTOR(S) WRITE LONG WRITE VERIFY READ VERIFY SECTOR(S) SEEK EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS...
Page 92 Interface Table 5.3 Command code and parameters (2 of 2) PARAMETER USED COMMAND CODE（Bit） COMMAND NAME FR SC SN CY DH READ BUFFER FLUSH CACHE WRITE BUFFER IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SECURITY SET PASSWORD SECURITY UNLOCK SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY DISABLE...
Page 93 5.3 Host Commands Notes: Features Register CY: Cylinder Registers Sector Count Register DH: Drive/Head Register SN: Sector Number Register Retry at error 1 = Without retry 0 = With retry Necessary to set parameters Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored.
Page 94 Interface 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) (CM) (DH) Head No.
Page 95 5.3 Host Commands SC: Sector Count register x, xx: Do not care (no necessary to set) Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
Page 96 Interface (1) RECALIBRATE (X’10’ to X’1F’) This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the BSY bit, and generates an interrupt.
Page 97: Read Sector(S) (X'20' Or X'21')
5.3 Host Commands (2) READ SECTOR(S) (X’20’ or X’21’) This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified from 1 to 256 sectors.
Page 98 Interface (R: Retry) At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 99: Read Long (X'22' Or X'23')
5.3 Host Commands (3) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
Page 100: Write Sector(S) (X'30' Or X'31')
Interface (4) WRITE SECTOR(S) (X’30’ or X’31’) This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified from 1 to 256 sectors.
Page 101 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 102: Write Long (X'32' Or X'33')
Interface (5) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
Page 103: Write Verify (X'3C')
5.3 Host Commands (6) WRITE VERIFY (X’3C’) This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.
Page 104: Read Verify Sector(S) (X'40' Or X'41')
Interface (7) READ VERIFY SECTOR(S) (X’40’ or X’41’) This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system. After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt.
Page 105: Seek (X'70' To X'7F')
5.3 Host Commands (8) SEEK (X’70’ to X’7F’) This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.
Page 106: Execute Device Diagnostic (X'90')
Interface (9) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.
Page 107 5.3 Host Commands attention: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting contents) (CM) Head No. /LBA [MSB] (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information Head No.
Page 108: Initialize Device Parameters (X'91')
Interface (10) INITIALIZE DEVICE PARAMETERS (X’91’) The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters.
Page 109: Download Micro Code (X'92')
5.3 Host Commands (11) DOWNLOAD MICRO CODE (X’92’) At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) Sector count (15-8) (SC) Sector count (7-0) (FR) Subcommand code At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH)
Page 110: Table 5.5 Operation Of Download Micro Code
Interface Table 5.5 Operation of DOWNLOAD MICRO CODE Host Command Movement of device Subcommand code Sector count Data transfer Microcode rewriting execution (FR Reg) (SN, SC Reg) 0000h Rewriting execution reservation xxxxh It is. Rewriting execution reservation 0000h Execution. ** xxxxh It is.
Page 111: Standby Immediate (X'94' Or X'e0')
5.3 Host Commands (12) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the APS timer function. At command issuance (I/O registers setting contents) (CM) X’94’...
Page 112: Idle Immediate (X'95' Or X'e1')
Interface (13) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the APS timer function. At command issuance (I/O registers setting contents) (CM) X’95’...
Page 113: Standby (X'96' Or X'e2')
5.3 Host Commands (14) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. If the device has already spun down, the spin-down sequence is not implemented.
Page 114: Idle (X'97' Or X'e3')
Interface (15) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates interrupt even if the device has not fully entered the idle mode.
Page 115 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E202-01EN 5-39...
Page 116: Check Power Mode (X'98' Or X'e5')
Interface (16) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value.
Page 117: Sleep (X'99' Or X'e6')
5.3 Host Commands (17) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.
Page 118: Smart (X'b0)
Interface (18) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued. Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register).
Page 119: Table 5.7 Features Register Values (Subcommands) And Functions
5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART READ DATE: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
Page 120 Interface Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART READ LOG: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.
Page 121 5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART RETURN STATUS: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.
Page 122 Interface At command issuance (I-O registers setting contents) (CM) (DH) (CH) Key (C2h) (CL) Key (4Fh) (SN) (SC) (FR) Subcommand At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h/2Ch) (CL) Key-failure prediction status (4Fh/F4h) (SN) (SC) (ER)
Page 123: Table 5.8 Format Of Device Attribute Value Data
5.3 Host Commands Table 5.8 Format of device attribute value data Byte Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far 07 to 0C Raw attribute value Reserved 0E to 169 Attribute 2 to (The format of each attribute value is the same as...
Page 124 Interface • Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same.
Page 125 5.3 Host Commands • Status Flag Meaning If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value. If this bit is 1 (0), it indicates the attribute only updated by an on- line test (off-line test).
Page 126: Table 5.10 Off-Line Data Collection Status
Interface Table 5.10 Off-line data collection status Status Byte Meaning 00h or 80h Off-line data acquisition is not executed. 02h or 82h Off-line data acquisition has ended without an error. 04h or 84h Off-line data acquisition is interrupted by a command from the host. 05h or 85h Off-line data acquisition has ended before completion because of a command from the host.
Page 127: Table 5.12 Off-Line Data Collection Capability
5.3 Host Commands • Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off- line data collection capability is 0, it indicates that off-line data collection is not supported. Table 5.12 Off-line data collection capability Meaning If this bit is 1, it indicates that the SMART EXECUTE OFF- LINE IMMEDATE sub-command (FR register = D4h) is...
Page 128: Table 5.14 Error Logging Capability
Interface • Error logging capability Table 5.14 Error logging capability Meaning If this bit is 1, it indicates that the drive error logging function is supported. 1 to 7 Reserved bits • Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.
Page 129 5.3 Host Commands • SMART error logging If the device detects an unrecoverable error during execution of a command received from the host, the device registers the error information in the SMART Summary Error Log (see Table 5.16) and the SMART Comprehensive Error Log (see Table 5.17), and saves the information on media.
Page 130: Table 5.16 Data Format Of Smart Summary Error Log
Interface Table 5.16 Data format of SMART Summary Error Log Byte Item Version of this function Pointer for the latest "Error Log Data Structure" 02 to 0D First command data structure 0E to 19 Second command data structure 1A to 25 Third command data structure 26 to 31 Fourth command data structure...
Page 131: Table 5.17 Data Format Of Smart Comprehensive Error Log
5.3 Host Commands • Command data structure Indicates the command received when an error occurs. • Error data structure Indicates the status register when an error occurs. • Total number of drive errors Indicates total number of errors registered in the error log. •...
Page 132: Table 5.18 Smart Self-Test Log Data Format
Interface • SMART Self-Test The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self-test. When the self-test is completed, the device saves the SMART self-test log to the disk medium.
Page 133: Table 5.19 Selective Self-Test Log Data Structure
5.3 Host Commands Table 5.19 Selective self-test log data structure Offset Description Initial 00h, 01h 01h, 00h Data Structure Revision Number 02h...09h Starting LBA 00h...00h Test Span 1 0Ah...11h Ending LBA 00h...00h 12h...19h Starting LBA 00h...00h Test Span 2 1Ah...21h Ending LBA 00h...00h 22h...29h...
Page 134: Table 5.20 Selective Self-Test Feature Flags
Interface • Feature Flags Table 5.20 Selective self-test feature flags Description Vendor specific (unused) When set to one, perform off-line scan after selective test Vendor specific (unused) When set to one, off-line scan after selective test is pending. When set to one, off-line scan after selective test is active. 5...15 Reserved Bit [l] shall be written by the host and returned unmodified by the device.
Page 135: Device Configuration (X'b1')
5.3 Host Commands (19) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these Features register values. If this command sets with the reserved value of Features register, an aborted error is posted.
Page 136 Interface • DEVICE CONFIGURATION RESTORE (FR = C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command.
Page 137 5.3 Host Commands bit. After execution of this command, the settings are kept for the device power down or reset. If the restriction of Multiword DMA modes or Ultra DMA modes is executed, a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued.
Page 138: Table 5.21 Device Configuration Identify Data Structure
Interface Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content X'0001' Data structure revision X'0007' Multiword DMA modes supported Reflected in IDENTIFY information "WORD63". Bit 15-3: Reserved Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0:...
Page 139: Read Multiple (X'c4')
5.3 Host Commands (20) READ MULTIPLE (X’C4’) The READ MULTIPLE Command performs the same as the READ SECTOR(S) Command except that when the device is ready to transfer data for a block of sectors, and enters the interrupt pending state only before the data transfer for the first sector of the block sectors.
Page 140 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)
Page 141: Write Multiple (X'c5')
5.3 Host Commands (21) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
Page 142 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) (ER) Error information...
Page 143: Set Multiple Mode (X'c6')
5.3 Host Commands (22) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.
Page 144 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) Sector count/block (ER) Error information 5-68 C141-E202-01EN...
Page 145: Read Dma (X'c8' Or X'c9')
5.3 Host Commands (23) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...
Page 146 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 147: Write Dma (X'ca' Or X'cb')
5.3 Host Commands (24) WRITE DMA (X’CA’ or X’CB’) This command operates similarly to the WRITE SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. •...
Page 148 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (SC) 00 (*1) (ER)
Page 149: Read Buffer (X'e4')
5.3 Host Commands (25) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
Page 150: Flush Cache (X'e7')
Interface (26) FLUSH CACHE (X’E7’) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred. The device performs every error recovery so that the data are read correctly.
Page 151: Write Buffer (X'e8')
5.3 Host Commands (27) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data.
Page 152: Identify Device (X'ec')
Interface (28) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information from the device. Upon receipt of this command, the drive sets the BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and generates an interrupt.
Page 153: Identify Device Dma (X'ee')
5.3 Host Commands (29) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
Page 154: Table 5.22 Information To Be Read By Identify Device Command
Interface Table 5.22 Information to be read by IDENTIFY DEVICE command (1 of 2) Word Value Description X’045A’ General Configuration *1 X’3FFF’ Number of Logical cylinders *2 X’xxxx’ Detailed Configuration *3 X’10’ Number of Logical Heads *2 X’0000’ Undefined X’3F’ Number of Logical sectors per Logical track *2 X’0000’...
Page 155 5.3 Host Commands Table 5.22 Information to be read by IDENTIFY DEVICE command (2 of 2) Word Value Description X’0078’ Manufacturer’s recommended DMA transfer cycle time : 120 [ns] X’00F0’ Minimum PIO transfer cycle time without IORDY flow control : 240 [ns] X’0078’...
Page 156 IDENTIFY DEVICE Valid = 0 Bit 1-0: Reserved *2 Word 1, 3, 6, 60-61 Word MHU2100AT X ' 3FFF ' X ' 10 ' X ' 3F ' 60-61 X ' BA52230 ' *3 Status of the Word 2 Identify information is shown as follows:...
Page 157 5.3 Host Commands *5 Word 50: Device capability Bit 15: Bit 14: Bit 13 to 1 Reserved Bit 0 Standby timer value '1' = Standby timer value of the device is the smallest value. *6 Word 51: PIO data transfer mode Bit 15-8: PIO data transfer mode X’02’=PIO mode 2...
Page 158 Interface *10 Word 64: Advance PIO transfer mode support status Bit 15-8: Reserved Bit 7-0: Advance PIO transfer mode Bit 1: 1 = Mode 4 Bit 0: 1 = Mode 3 *11 WORD 80 Bit 15-7: Reserved Bit 6: 1 = ATA/ATAPI-6 supported Bit 5: 1 = ATA/ATAPI-5 supported Bit 4:...
Page 159 5.3 Host Commands *13 WORD 83 Bit 15: Bit 14: Bit 13: * '1' = FLUSH CACHE EXT command supported. Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10:* '1' = 48 bit LBA feature set.
Page 160 Interface *15 WORD 85 Bit 15: Undefined. Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command. Bit 12: '1' = Supports the WRITE BUFFER command. Bit 11: Undefined. Bit 10: '1' = Supports the Host Protected Area function. Bit 9: '1' = Supports the DEVICE RESET command.
Page 161 Bit 2: '1' = Supports the Mode 2 Bit 1: '1' = Supports the Mode 1 Bit 0: '1' = Supports the Mode 0 *19 WORD 89 MHU2100AT = X'32': 100 minutes *20 WORD 93 Bits 15: Bit 14: = '1' Bit 13: '1' = CBLID- is a higher level than VIH (80-conductor cable).
Page 162 Interface Bit 10, 9: Method for deciding the device No. of Device 1. '00' = Reserved '01' = Using a jumper. '10' = Using the CSEL signal. '11' = Other method. Bit 8: = '1' (In the case of device 1) Bits 7-0: In the case of Device 0 (master drive), a valid value is set.
Page 163 5.3 Host Commands *23 WORD 128 Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-6: Reserved Bit 5: '1' = Enhanced security erase supported Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2: '1' = Security locked Bit 1:...
Page 164: Set Features (X'ef')
Interface (30) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register.
Page 165 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or *1~3 (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information *1) Data Transfer Mode...
Page 166 Interface Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) 01000 101 (X’45’: Mode 5)
Page 167 5.3 Host Commands *3) Automatic Acoustic Management (AAM) The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h, and then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets.
Page 168: Security Set Password (X'f1')
Interface (31) SECURITY SET PASSWORD (X’F1’) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.24 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
Page 169 5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E202-01EN 5-93...
Page 170: Security Unlock(X'f2')
Interface (32) SECURITY UNLOCK(X’F2’) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.26 to the device. Operation of the device varies as follows depending on whether the host specifies the master password. • When the master password is selected When the security level is LOCKED MODE is high, the password is compared with the master password already set.
Page 171 5.3 Host Commands At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E202-01EN 5-95...
Page 172: Security Erase Prepare (X'f3')
Interface (33) SECURITY ERASE PREPARE (X’F3’) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
Page 173: Security Erase Unit (X'f4')
5.3 Host Commands (34) SECURITY ERASE UNIT (X’F4’) This command erases all user data. This command also invalidates the user password and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set.
Page 174: Security Freeze Lock (X'f5')
Interface (35) SECURITY FREEZE LOCK (X’F5’) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE. • SECURITY SET PASSWORD • SECURITY UNLOCK •...
Page 175 5.3 Host Commands At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E202-01EN 5-99...
Page 176: Security Disable Password (X'f6')
Interface (36) SECURITY DISABLE PASSWORD (X’F6’) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.
Page 177 5.3 Host Commands At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information C141-E202-01EN 5-101...
Page 178: Read Native Max Address (X'f8')
Interface (37) READ NATIVE MAX ADDRESS (X’F8’) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers.
Page 179: Set Max (X'f9')
5.3 Host Commands (38) SET MAX (X’F9’) SET MAX Features Register Values Value Command Obsolete SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK 05h - FFh Reserved • SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command.
Page 180 Interface At command issuance (I/O registers setting contents) (CM) (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB]...
Page 181 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Password information Words Contents Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved • SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
Page 182 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information • SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.
Page 183 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information • SET MAX FREEZE LOCK (FR = 04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
Page 184 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information 5-108 C141-E202-01EN...
Page 185: Read Sector(S) Ext (X'24'): Option (Customizing)
5.3 Host Commands (39) READ SECTOR(S) EXT (X’24’): Option (customizing) • Description This command is the extended command of the READ SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 186: Read Dma Ext (X'25'): Option (Customizing)
Interface (40) READ DMA EXT (X’25’): Option (customizing) • Description This command is the extended command of the READ DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 187: Read Native Max Address Ext (X'27H'): Option (Customizing)
5.3 Host Commands (41) READ NATIVE MAX ADDRESS EXT (X’27’): Option (customizing) • Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1.
Page 188: Read Multiple Ext (X'29'): Option (Customizing)
Interface (42) READ MULTIPLE EXT (X’29’): Option (customizing) • Description This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 189: Read Log Ext (X'2F') [Optional Command (Customize)]
5.3 Host Commands (43) READ LOG EXT (X'2F') [Optional command (Customize)] • Description This command reads data from the general-purpose log of a device. The general- purpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. The types of logs available depend on the customize operation.
Page 190 Interface Log address: Log number of the log to be read Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be read from the specified log If the device does not support this command, the device shall return the Command Aborted error.
Page 191: Write Sector(S) Ext (X'34'): Option (Customizing)
5.3 Host Commands (44) WRITE SECTOR(S) EXT (X’34’): Option (customizing) • Description This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 192: Write Dma Ext (X'35'): Option (Customizing)
Interface (45) WRITE DMA EXT (X’35’): Option (customizing) • Description This command is the extended command of the WRITE DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 193: Set Max Address Ext (X'37'): Option (Customizing)
5.3 Host Commands (46) SET MAX ADDRESS EXT (X’37’): Option (customizing) • Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode. The address information specified with this command is set in words 1, 54, 57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response.
Page 194 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) P SET MAX LBA (47-40) (CH) C SET MAX LBA (23-16) (CL) P SET MAX LBA (39-32) (CL) C SET MAX LBA (15-8) (SN) P SET MAX LBA (31-24) (SN) C SET MAX LBA (7-0) (SC) P...
Page 195: Write Multiple Ext (X'39'): Option (Customizing)
5.3 Host Commands (47) WRITE MULTIPLE EXT (X’39’): Option (customizing) • Description This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 196: Write Log Ext (X'3F') [Optional Command (Customize)]
Interface (48) WRITE LOG EXT (X’3F’) [Optional command (Customize)] • Description This command writes data to the general-purpose log of a device. The general- purpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. However, some of these logs are read-only logs.
Page 197 5.3 Host Commands Log address: Log number of the log to be written Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be written to the specified log If the device does not support this command, the device shall return the Command Aborted error.
Page 198: Read Verify Sector(S) Ext (X'42): Option (Customizing)
Interface (49) READ VERIFY SECTOR(S) EXT (X’42): Option (customizing) • Description This command is the extended command of the READ VERIFY SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
Page 199: Flush Cache Ext (X'ea'): Option (Customizing)
5.3 Host Commands (50) FLUSH CACHE EXT (X’EA’): Option (customizing) • Description This command executes the same operation as the Flush Cache command (E7h) but only LBA = 1 can be specified. • Error reporting conditions This command is issued with LBA = 0. (ST = 51h, ER= 10h: Aborted) At command issuance (I/O registers setting contents) (CM) (DH)
Page 200: Error Posting
Interface 5.3.3 Error posting Table 5.27 lists the defined errors that are valid for each command. Table 5.27 Command code and parameters (1 of 2) Error Register (X '1F1') Status Register (X '1F7') COMMAND NAME ICRC IDNF ABRT TK0NF DRDY RECALIBRATE READ SECTOR(S) READ LONG...
Page 201 5.3 Host Commands Table 5.27 Command code and parameters (2 of 2) Error Register (X '1F1') Status Register (X '1F7') COMMAND NAME ICRC IDNF ABRT TK0NF DRDY READ SECTOR(S) EXT READ DMA EXT V *2 READ NATIVE MAX ADDRESS READ MULTIPLE EXT READ LOG EXT WRITE SECTOR(S) EXT WRITE DMA EXT...
Page 202: Command Protocol
Interface 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1.
Page 203: Figure 5.3 Read Sector(S) Command Protocol
5.4 Command Protocol The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are repeated. Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit.
Page 204: Figure 5.4 Protocol For Command Abort
Interface IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
Page 205: Pio Data Transferring Commands From Host To Device
5.4 Command Protocol 5.4.2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive. • WRITE SECTOR(S) (EXT) • WRITE LONG • WRITE VERIFY • DOWNLOAD MICROCODE •...
Page 206: Figure 5.5 Write Sector(S) Command Protocol
Interface 40 ms Figure 5.5 WRITE SECTOR(S) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
Page 207: Commands Without Data Transfer
5.4 Command Protocol 5.4.3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device. • RECABLIBRATE • READY VERIFY SECTOR(S) (EXT) • SEEK • EXECUTE DEVICE DIAGNOSTIC • INITIALIZE DEVICE PARAMETERS •...
Page 208: Other Commands
Interface Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands • READ MULTIPLE (EXT) • WRITE MULTIPLE (EXT) • SLEEP See the description of each command. 5.4.5 DMA data transfer commands • READ DMA (EXT) • WRITE DMA (EXT) •...
Page 209: Figure 5.7 Normal Dma Data Transfer
5.4 Command Protocol When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA data transfer C141-E202-01EN 5-133...
Page 210: Ultra Dma Feature Set
Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.
Page 211: Phases Of Operation
5.5 Ultra DMA Feature Set Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command.
Page 212: The Data In Transfer
Interface 7) The host shall release DD (15:0) within t after asserting DMACK-. 8) The device may assert DSTROBE t after the host has asserted DMACK-. ZIORDY Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.
Page 213: Terminating An Ultra Dma Data In Burst
5.5 Ultra DMA Feature Set 2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges. NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t before asserting STOP.
Page 214 Interface 6) The host shall drive DD (15:0) no sooner than t after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP.
Page 215 5.5 Ultra DMA Feature Set 4) If the host negates HDMARDY- within t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
Page 216: Ultra Dma Data Out Commands
Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
Page 217: The Data Out Transfer
5.5 Ultra DMA Feature Set 5.5.4.2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements): 1) The host shall drive a data word onto DD (15:0). 2) The host shall generate an HSTROBE edge to latch the new word no sooner than t after changing the state of DD (15:0).
Page 218: Terminating An Ultra Dma Data Out Burst
Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
Page 219 5.5 Ultra DMA Feature Set b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
Page 220: Ultra Dma Crc Rules
Interface 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.
Page 221: Series Termination Required For Ultra Dma
5.5 Ultra DMA Feature Set The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.
Page 222: Timing
Interface 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Min. Max. Unit Cycle time — Data register selection setup time for DIOR-/DIOW- —...
Page 223: Multiword Data Transfer
5.6 Timing 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. DMACK- DIOR-/DIOW- Symbol Timing parameter Min. Max. Unit Cycle time — Pulse width of DIOR-/DIOW- — Data Access time for DIOR- —...
Page 224: Ultra Dma Data Transfer
Interface 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.23 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Page 225: Ultra Dma Data Burst Timing Requirements
5.6 Timing 5.6.3.2 Ultra DMA data burst timing requirements Table 5.29 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT...
Page 226 Interface Table 5.29 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Limited interlock time (*1) Interlock time with minimum (*1) Unlimited interlock time (*1)
Page 227: Table 5.30 Ultra Dma Sender And Recipient Timing Requirements
5.6 Timing Table 5.30 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 Recipient IC data setup time (from DSIC...
Page 228: Sustained Ultra Dma Data In Burst
Interface 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC 2CYC DSTROBE at device DVHIC DVSIC DVHIC DVSIC DVHIC DD(15:0) at device DSTROBE at host DHIC DHIC DHIC DSIC DSIC...
Page 229: Host Pausing An Ultra Dma Data In Burst
5.6 Timing 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
Page 230: Device Terminating An Ultra Dma Data In Burst
Interface 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
Page 231: Host Terminating An Ultra Dma Data In Burst
5.6 Timing 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are...
Page 232: Initiating An Ultra Dma Data Out Burst
Interface 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DZFS DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 233: Sustained Ultra Dma Data Out Burst
5.6 Timing 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC HSTROBE 2CYC at host DVHIC DVHIC DVHIC DVSIC DVSIC DD(15:0) at host HSTROBE at device DHIC DSIC DHIC DSIC...
Page 234: Device Pausing An Ultra Dma Data Out Burst
Interface 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY- is negated.
Page 235: Host Terminating An Ultra Dma Data Out Burst
5.6 Timing 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 236: Device Terminating An Ultra Dma Data Out Burst
Interface 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
Page 237: Power-On And Reset
5.6 Timing 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device]...
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Page 239: Chapter 6 Operations
CHAPTER 6 Operations Device Response to the Reset Power Save Defect Processing Read-ahead Cache Write Cache C141-E202-01EN...
Page 240: Operations
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for least 500 ms to confirm presence of a slave device (device 1).
Page 241: Response To Hardware Reset
6.1 Device Response to the Reset Power on Master device Power On Reset- Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to If presence of a slave device is 500 ms. confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On Reset- BSY bit...
Page 242: Figure 6.2 Response To Hardware Reset
Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 450 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. The asserted PDIAG-signal is negated 30 seconds after it is asserted if the command is not received.
Page 243: Response To Software Reset
6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.
Page 244: Response To Diagnostic Command
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.
Page 245: Power Save
6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active.
Page 246 Operations • Upon receipt of a hard reset • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active, active idle, or low power idle mode because the access to the disk medium cannot be made immediately.
Page 247: Power Commands
6.3 Defect Processing 6.2.2 Power commands The following commands are available as power commands. • IDLE • IDLE IMMEDIATE • STANDBY • STANDBY IMMEDIATE • SLEEP • CHECK POWER MODE • SET FEATURES (APM setting) 6.3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information.
Page 248: Alternating Processing For Defective Sectors
Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Sector slip processing In this method, defective sectors are not used (thereby avoiding the effects of defects), and each defective sector is assigned to the next contiguous sector that is normal.
Page 249: Figure 6.6 Automatic Alternating Processing
6.3 Defect Processing (3) Automatic alternating processing This technology assigns a defective sector to a spare sector of an spare cylinder for alternate assignment. This device performs automatic alternating processing in the event of any of the following errors. • Automatic alternating processing is attempted for read error recovery by reaching the specified retry cycle while a read error retry is in progress.
Page 250: Read-Ahead Cache
Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead data, data on the data buffer can be transferred without accessing the disk media.
Page 251: Caching Operation
6.4 Read-ahead Cache 6.4.2 Caching operation The caching operation is performed only when the commands listed below are received. If any of the following data are stored on the data buffer, the data is sent to the host system. • All of the sector data that this command processes.
Page 252 Operations 1)-1 Any command other than the following commands is issued. (All caching- target data is invalidated.) RECALIBRATE READ LONG WRITE LONG IDLE IMMEDIATE DOWNLOAD MICROCODE DEVICE CONFIGURATION READ BUFFER WRITE BUFFER SET FEATURES SECURITY ERASE UNIT READ LOG EXT WRITE LOG EXT UNSUPPORT COMMAND (INVALID COMMAND) 1)-2 Commands that partially invalidate caching data...
Page 253: Using The Read Segment Buffer
6.4 Read-ahead Cache 6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations. 6.4.3.1 Miss-hit In this situations, the top block of read requested data is not stored at all in the data buffer.
Page 254: Sequential Hit
Operations 6.4.3.2 Sequential Hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed, the read command transmits the Read requested data to the host system continuing read-ahead without newly allocating the buffer for read.
Page 255: Full Hit
6.4 Read-ahead Cache 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data is started from the location where hit data is stored. For data that is a target of caching and remains before a full hit, the data is retained when execution of the command is completed.
Page 256: Partial Hit
Operations 6.4.3.4 Partial hit In this situation, a part of read requested data including the top sector is stored in the data buffer. A transfer of the read requested data starts from the address where the data that is hit is stored until the top sector of the read requested data. Remaining part of insufficient data is read then.
Page 257: Write Cache
6.5 Write Cache 6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media. When Write Cache is permitted, the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer.
Page 258 Operations (3) Status report in the event of an error The status report concerning an error occurring during writing onto media is created when the next command is issued. Where the command reporting the error status is not executed, only the error status is reported. Only the status of an error that occurs during write processing is reported.
Page 259 6.5 Write Cache IMPORTANT If Write Cache is enabled, there is a possibility that data transferred from the host with the Write Cache enable command is not completely written on disk media before the normal end interrupt is issued. If an unrecoverable error occurs while multiple commands that are targets of write caching are received, the host has difficulty determining which command caused the error.
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Page 261: Glossary
Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
Page 262 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Page 263 Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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Page 265: Acronyms And Abbreviations
Acronyms and Abbreviations Hard disk drive ABRT Aborted command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...
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Page 267 Index 1 drive connection ........2-3 check sum ......5-52, 5-55, 5-56 2 drives configuration........ 2-4 circuit configuration......4-3, 4-5 2 drives connection........2-4 command block register......5-8 8MB buffer ..........6-12 command code and parameter ..5-14, 5-15, 5-16, 5-124, 5-125 command data structure ......5-55 command description.......5-18 A/D converter circuit.......
Page 268 Index data that is a target of caching ....6-13 example of model name and product data transfer mode........5-89 number............1-5 data-surface servo format ......4-15 EXECUTE DEVICE DIAGNOSTIC ..5-30 defect processing ........6-9 execution example of READ description ..... 5-109, 5-110, 5-111, MULTIPLE command ......5-63 5-112, 5-113, 5-115, 5-116, 5-117, execution timing of self-calibration ...4-8 5-119, 5-120, 5-122, 5-123...
Page 269 Index Fujitsu Internal Use Only multiword data transfer......5-147 multiword DMA data transfer timing ..5-147 I/O register..........5-7 IDENTIFY DEVICE....... 5-76 IDENTIFY DEVICE DMA..... 5-77 IDLE..........5-38, 6-9 normal DMA data transfer .....5-133 IDLE IMMEDIATE ......5-36, 6-9 Information to be read by IDENTIFY DEVICE command.....5-78, 5-79...
Page 270 Index selective self-test feature flag....5-58 selective self-test log data structure ..5-57 raw attribute value ........5-49 selective self-test pending time ....5-58 READ BUFFER ........5-73 self-calibration ...........4-7 read circuit ..........4-10 self-calibration content.......4-7 READ DMA ..........5-69 self-diagnosis ..........1-3 READ DMA (EXT).........6-12 self-test execution status ....5-50, 5-56 READ DMA EXT .........5-110 self-test index ...........5-56 READ LOG EXT ........5-113...
Page 271 Index Fujitsu Internal Use Only STANDBY command ....... 6-8 in command........5-135 STANDBY IMMEDIATE ....5-35, 6-9 out command........5-140 STANDBY IMMEDIATE command..6-8 ultra DMA data burst timing standby mode..........6-8 requirement ........5-149 start mode ..........4-19 ultra DMA data transfer ......5-148 status............
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Page 273 Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E202-01EN Manual name MHU2100AT DISK DRIVE PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance Illustration Technical level Glossary Organization Acronyms & Abbreviations...
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Page 275 MHU2100AT DISK DRIVE PRODUCT MANUAL C141-E202-01EN MHU2100AT DISK DRIVE PRODUCT MANUAL C141-E202-01EN...
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Fujitsu MHU2100AT Product Manual

CHAPTER 1 Device Overview

CHAPTER 2 Device Configuration

CHAPTER 3 Installation Conditions

CHAPTER 4 Theory of Device Operation

CHAPTER 5 Interface

CHAPTER 6 Operations

Glossary

Acronyms and Abbreviations

Quick Links

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Summary of Contents for Fujitsu MHU2100AT