Table of Contents
Advertisement
(22) WRITE DMA (X'CA' or X'CB')
This command operates similarly to the WRITE SECTOR(S) command except for
following events.
The data transfer starts at the timing of DMARQ signal assertion.
•
The device controls the assertion or negation timing of the DMARQ signal.
•
The device posts a status as the result of command execution only once at
•
completion of the data transfer or completion of processing in the device.
The device posts a status as the result of command execution only once at
•
completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command
execution cannot be continued is detected, the data transfer is stopped without
transferring data of sectors after the erred sector. The device generates an interrupt
using the INTRQ signal and posts a status to the host system. The format of the
error information is the same as the WRITE SECTOR(S) command.
A host system can select the following transfer mode using the SET FEATURES
command.
Multiword DMA transfer mode 0 to 2
•
Ultra DMA transfer mode 0 to 5
•
At command issuance (I/O registers setting contents)
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
C141-E258
1
1
0
0
x
L
x
DV
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
5.3 Host Commands
1
0
1
R
Start head No. / LBA
[MSB]
5-71
Advertisement
Table of Contents
