Ultra Dma Data Burst Timing Requirements; Table 5.16 Ultra Dma Data Burst Timing Requirements - Fujitsu MHC2032AT Product Manual

5.6.4.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2)
NAME MODE 0
(in ns)
MIN MAX
t 114
CYC
t2 235
CYC
t 15
DS
t 3
DH
t 70
DVS
t 6
DVH
t 0 230
FS
t 0 150
LI
t 20
MLI
t 0
UI
t 10
AZ
t 20
ZAH
t 0
ZAD
t 20 70
ENV
t 50
SR
C141-E050-02EN
MODE 1 MODE 2
(in ns) (in ns)
MIN MAX MIN MAX
75 55
156 117
10 7
3 3
48 34
6 6
0 200 0
0 150 0
20 20
0 0
10
20 20
0 0
20 70 20
30
COMMENT
Cycle time (from STROBE edge to
STROBE edge)
Two cycle time (from rising edge to next
rising edge or from falling edge to next
falling edge of STROBE)
Data setup time (at recipient)
Data hold time (at recipient)
Data valid setup time at sender (from data
bus being valid until STROBE edge)
Data valid hold time at sender (from
STROBE edge until data may become
invalid)
170 First STROBE time (for device to first
negate DSTROBE from STOP during a
data in burst)
150 Limited interlock time (see Note 1)
Interlock time with minimum (see Note 1)
Unlimited interlock time (see Note 1)
10 Maximum time allowed for output drivers
to release (from being asserted or negated)
Minimum delay time required for
output drivers to assert or negate (from
released state)
70 Envelope time (from DMACK- to STOP
and HDMARDY- during data in burst
initiation and from DMACK to STOP
during data out burst initiation)
20 STROBE-to-DMARDY-time (if DMARDY-
is negated before this long after STROBE
edge, the recipient shall receive no more than
one additional data word)
5.6 Timing
5-97