Fujitsu MHJ2181AT Product Manual
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Fujitsu MHJ2181AT Product Manual

Fujitsu MHJ2181AT Product Manual

Fujitsu computer drive user manual
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C141-E088-03EN
MHJ2181AT, MHK2120AT,
MHK2090AT, MHK2060AT
DISK DRIVES
PRODUCT MANUAL

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Summary of Contents for Fujitsu MHJ2181AT

  • Page 1 C141-E088-03EN MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES PRODUCT MANUAL...
  • Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
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  • Page 4: Revision History

    Edition Date Revised section (*1) (Added/Deleted/Altered) 1999-07-20 1999-08-30 Chapter 1 (Altered) Chapter 4 (Altered) 1999-10-15 Chapter 1 (altered) *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E088-03EN Revision History — • Shock and vibration specifications for MHJ series added to the Table 1.6.
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  • Page 6 This manual describes the MHJ Series and MHK Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

  • Page 7: Operating Environment

    Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: In the text, the alert signal is centered, followed below by the indented message.
  • Page 8 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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  • Page 10: Important Alert Items

    Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the predate or other property, may occur if the user does not perform the procedure correctly.
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  • Page 12: Manual Organization

    Manual Organization MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES PRODUCT MANUAL (C141-E088) <This manual> MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES MAINTENANCE MANUAL (C141-F038) C141-E088-03EN • Device Overview • Device Configuration • Installation Conditions • Theory of Device Operation • Interface • Operations •...
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  • Page 14: Table Of Contents

    CHAPTER 1 Device Overview... 1-1 Features 1.1.1 Functions and performance 1.1.2 Adaptability 1.1.3 Interface Device Specifications 1.2.1 Specifications summary 1.2.2 Model and product number Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects CHAPTER 2 Device Configuration...
  • Page 15 Contents CHAPTER 3 Installation Conditions...3-1 Dimensions Mounting Cable Connections 3.3.1 Device connector 3.3.2 Cable connector specifications 3.3.3 Device connection 3.3.4 Power supply connector (CN1) Jumper Settings 3.4.1 Location of setting jumpers 3.4.2 Factory default setting 3.4.3 Master drive-slave drive setting 3.4.4 CSEL setting CHAPTER 4 Theory of Device Operation...4-1...
  • Page 16 4.6.1 Read/write preamplifier (PreAMP) 4.6.2 Write circuit 4.6.3 Read circuit 4.6.4 Digital PLL circuit Servo Control 4.7.1 Servo control circuit 4.7.2 Data-surface servo format 4.7.3 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control CHAPTER 5 Interface ... 5-1 Physical Interface 5.1.1 Interface signals 5.1.2 Signal assignment on the connector...
  • Page 17 Contents 5.5.2 Phases of operation 5.5.2.1 Ultra DMA burst initiation phase 5.5.2.2 Data transfer phase 5.5.2.3 Ultra DMA burst termination phase 5.5.3 Ultra DMA data in commands 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.4 Terminating an Ultra DMA data in burst 5.5.4 Ultra DMA data out commands...
  • Page 18 CHAPTER 6 Operations ... 6-1 Device Response to the Reset 6.1.1 Response to power-on 6.1.2 Response to hardware reset 6.1.3 Response to software reset 6.1.4 Response to diagnostic command Address Translation 6.2.1 Default parameters 6.2.2 Logical address Power Save 6.3.1 Power save mode 6.3.2 Power commands Defect Management 6.4.1 Spare area...
  • Page 19 Figure 3.1 Dimensions (MHJ/MHK series) Figure 3.2 Orientation (Sample: MHJ2181AT) Figure 3.3 Mounting frame structure Figure 3.4 Location of breather Figure 3.5 Surface temperature measurement points (Sample: MHJ2181AT) Figure 3.6 Service area (Sample: MHJ2181AT) Figure 3.7 Connector locations (Sample: MHJ2181AT) Figure 3.8 Cable connections Figure 3.9 Power supply connector pins (CN1)
  • Page 20 Figure 5.4 Protocol for command abort Figure 5.5 WRITE SECTOR(S) command protocol Figure 5.6 Protocol for the command execution without data transfer Figure 5.7 Normal DMA data transfer Figure 5.8 An example of generation of parallel CRC Figure 5.9 Ultra DMA termination with pull-up or pull-down Figure 5.10 Data transfer timing Figure 5.11 Multiword DMA data transfer timing (mode 2) Figure 5.12 Starting of Ultra DMA data In Burst transfer...
  • Page 21 Contents Table 3.2 Cable connector specifications Table 4.1 Self-calibration execution timechart Table 4.2 Write precompensation algorithm Table 5.1 Signal assignment on the interface connector Table 5.2 I/O registers Table 5.3 Command code and parameters Table 5.4 Information to be read by IDENTIFY DEVICE command Table 5.5 Features register values and settable modes Table 5.6...

  • Page 22: Chapter 1 Device Overview

    CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MHJ Series and MHK Series are 2.5-inch hard disk drives with built-in disk controllers.

  • Page 23: Features

    The fillowing features of the MHJ Series and MHK Series are described. (1) Compact The MHJ2181AT has 3 disks, and its height is 12.5 mm (0.492 inch). The MHK2120AT, MHK2090AT and MHK2060AT have 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

  • Page 24: Interface

    1.1.3 Interface (1) Connection to interface With the built-in ATA interface controller, the disk drives (the MHJ Series and MHK Series) can be connected to an ATA interface of a personal computer. (2) 512-KB data buffer The disk drives (the MHJ Series and MHK Series) uses a 512-KB data buffer to transfer data between the host and the disk media.

  • Page 25: Device Specifications

    Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specfications of the disk drives (MHJ Series and MHK Series). Table 1.1 Specifications (1/2) MHJ2181AT Format Capacity (*1) Number of Heads Number of Cylinders (User) Number of Sectors (User)

  • Page 26: Model And Product Number

    Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows. Table 1.1 Specifications (2/2) Model Formatted Capacity MHJ2181AT 8.45 GB MHK2120AT 8.45 GB MHK2090AT 8.45 GB MHK2060AT 6.00 GB 1.2.2 Model and product number...

  • Page 27: Figure 1.1 Current Fluctuation (Typ.) At +5V When Power Is Turned On

    Device Overview (3) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation. Table 1.3 Current and power dissipation Typical RMS Current MHJ Series Spin up (*1) 0.9 A Idle 170 mA R/W (on track) (*2) 460 mA Seek (*5) 460 mA Standby...

  • Page 28: Environmental Specifications

    (5) Power on/off sequence The voltage detector circuits (the MHJ Series and MHK Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 29: Acoustic Noise

    Device Overview 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Sound Pressure • Idle mode (DRIVE READY) Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Item Vibration (swept sine, one octave per minute)

  • Page 30: Reliability

    Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h MTBF is defined as follows: Total operation time in all fields MTBF= number of device failure in all fields (*1) *1 “Disk drive defects” refers to defects that involve repair, readjustment, or replacement.

  • Page 31: Error Rate

    Device Overview 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...

  • Page 32: Chapter 2 Device Configuration

    CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E088-03EN...

  • Page 33: Device Configuration

    The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. The number of disks used varies with the model, as described below. The disks are rated at over 50,000 start/stop operations. MHJ2181AT: 3 disks MHK2120AT: 2 disks (2) Head The heads are of the contact start/stop (CSS) type.

  • Page 34: Figure 2.2 Configuration Of Disk Media Heads

    Head Head MHJ2181AT MHK2120AT Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head.

  • Page 35: System Configuration

    Figure 2.3 1 drive system configuration 2.2.3 2 drives connection Note: When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration MHJ2181AT MHK2120AT MHC2032AT (Host adaptor) MHK2090AT MHC2040AT...
  • Page 36 2.2 System Configuration HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-4 interface. At high speed data transfer (PIO mode 3, mode 4, or DMA mode 2 U-DMA mode 4), occurence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
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  • Page 38: Chapter 3 Installation Conditions

    CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. C141-E088-03EN...

  • Page 39: Dimensions

    Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions (MHJ series) (1/2) C141-E088-03EN...
  • Page 40 3.1 Dimensions Figure 3.1 Dimensions (MHK series) (2/2) C141-E088-03EN...

  • Page 41: Mounting

    3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. (a) Horizontal –1 (c) Vertical –1 (e) Vertical –3 Figure 3.2 Orientation (Sample: MHJ2181AT) gravity (b) Horizontal –1 gravity (d) Vertical –2 gravity (f) Vertical –4...

  • Page 42: Figure 3.3 Mounting Frame Structure

    (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 5 kgcm. When attaching the HDD to the system frame, do not allow the system frame to touch parts (cover and base) other than parts to which the HDD is attached.

  • Page 43: Figure 3.4 Location Of Breather

    Installation Conditions Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4 in both MHJ series and MHK series. For breather hole of Figure 3.4, at least, do not allow its around 3 to block.

  • Page 44: Figure 3.5 Surface Temperature Measurement Points (Sample: Mhj2181At)

    DE. Regardless of the ambient temperature, this surface temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the temperature measurement point. Figure 3.5 Surface temperature measurement points (Sample: MHJ2181AT) Table 3.1 Surface temperature measurement points and standard values C141-E088-03EN...

  • Page 45: Figure 3.6 Service Area (Sample: Mhj2181At)

    Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Figure 3.6 Service area (Sample: MHJ2181AT) Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

  • Page 46: Cable Connections

    3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.7 Connector locations (Sample: MHJ2181AT) C141-E088-03EN 3.3 Cable Connections...

  • Page 47: Cable Connector Specifications

    Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications ATA interface and power supply cable (44-pin type) For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.

  • Page 48: Power Supply Connector (Cn1)

    3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). Figure 3.9 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.10 shows the location of the jumpers to select drive configuration and functions.

  • Page 49: Factory Default Setting

    Installation Conditions 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. Figure 3.11 Factory default setting 3.4.3 Master drive-slave drive setting Master device (device #0) or slave device (device #1) is selected. Open Open (a) Master drive Figure 3.12 Jumper setting of master or slave device Note: Pins A and C should be open.

  • Page 50: Csel Setting

    3.4.4 CSEL setting Figure 3.13 shows the cable select (CSEL) setting. Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 and 3.15 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level.

  • Page 51: Figure 3.15 Example (2) Of Cable Select

    Installation Conditions Figure 3.15 Example (2) of Cable Select 3-14 C141-E088-03EN...

  • Page 52: Chapter 4 Theory Of Device Operation

    CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

  • Page 53: Outline

    4.2.1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm. The MHJ2181AT have three disks and MHK2120AT and MHK2090AT have two disks and MHK2060AT have one disk. The head contacts the disk each time the disk rotation stops; the life of the disk is 50,000 contacts or more.

  • Page 54: Spindle

    Head MHJ2181AT MHK2120AT 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm 1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.

  • Page 55: Circuit Configuration

    Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

  • Page 56: Figure 4.2 Circuit Configuration

    4.3 Circuit Configuration 16 bit Figure 4.2 Circuit Configuration C141-E088-03EN...

  • Page 57: Power-On Sequence

    Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

  • Page 58: Self-Calibration

    Figure 4.3 Power-on operation sequence 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM tarque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.

  • Page 59: Execution Timing Of Self-Calibration

    Theory of Device Operation The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varing by the cylinder, the disk is divided into 23 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.

  • Page 60: Command Processing During Self-Calibration

    Table 4.1 Self-calibration execution timechart At power-on About 5 minutes About 5 minutes About 10 minutes About 10 minutes About 15 minutes About 15 minutes Every about 30 minutes 4.5.3 Command processing during self-calibration If the disk drive receives a command execution request from the host while executing self-calibration according to the timechart, the disk drive terminates self-calibration and starts executing the command precedingly.

  • Page 61: Write Circuit

    Theory of Device Operation signal (WUS) when a write error occurs due to head short-circuit or head disconnection. The Pre AMP sets the write current and bias current which flows through MR devices. 4.6.2 Write circuit The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC.

  • Page 62: Figure 4.4 Read/Write Circuit Block Diagram

    Figure 4.4 Read/write circuit block diagram C141-E088-03EN 4.6 Read/write Circuit MEEPR Viterbi Detect 16/17 ENDEC RWCLK SRV_CLK SRV_OUT[1:0] 4-11...

  • Page 63: Read Circuit

    Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 64: Digital Pll Circuit

    (3) Flash digitizer circuit This circuit is 10-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit.

  • Page 65: Servo Control

    Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
  • Page 66 The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

  • Page 67: Figure 4.7 Physical Sector Servo Configuration On Disk Surface

    Theory of Device Operation Figure 4.7 Physical sector servo configuration on disk surface 4-16 Servo frame (66 servo frames revolution) Diameter CYL-n (n: even number) direction Circumference direction Erase: DC erase area C141-E088-03EN...

  • Page 68: Index

    (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. SERVO A, SERVO B, SERVO C and SERVO D burst signals shown in Figure 4.8 followed the servo mark, cylinder gray and index information are output from the servo area on the data surface via the data head.

  • Page 69: Data-Surface Servo Format

    Theory of Device Operation 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

  • Page 70: Actuator Motor Control

    (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area gererates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.

  • Page 71: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
  • Page 72 d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection. e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a sepcific period, the MPU resets the SVC and starts from the beginning.
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  • Page 74: Chapter 5 Interface

    CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E088-03EN...

  • Page 75: Physical Interface

    Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS D IOR-: I/O READ H D M A R D Y : DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE: DATA STROBE DURING ULTRA DMA DATA OUT BURSTS INTRQ: PDIAG-: PASSED DIAGNOSTICS...

  • Page 76: Signal Assignment On The Connector

    5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal MSTR unused (KEY) RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DMARQ DIOW-, STOP DIOR-, HDMRDY, HSTROBE...
  • Page 77 Interface [signal] [I/O] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting Pin A, B Short: RESET- Reset signal from the host. This signal is low active and is asserted for a minimum of 25 s during power on.
  • Page 78 [signal] [I/O] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers. DA 0-2 Binary decoded address signals asserted by the host to access task file registers.

  • Page 79: Logical Interface

    Interface [signal] [I/O] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.

  • Page 80: I/O Registers

    5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

  • Page 81: Command Block Registers

    Interface 5.2.2 Command block registers (1) Data register (X’1F0’) The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode. (2) Error register (X’1F1’) The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
  • Page 82 [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Register Compare Error X’03’: Data Buffer Compare Error. X’05’: ROM Sum Check Error. X’80’: Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’...
  • Page 83 Interface (6) Cylinder Low register (X’1F4’) The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indcates LBA bits 15 to 8.
  • Page 84 (9) Status register (X’1F7’) The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid.
  • Page 85 Interface - Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected. If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

  • Page 86: Control Block Registers

    5.2.3 Control block registers (1) Alternate Status register (X’3F6’) The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

  • Page 87: Command Code And Parameters

    Interface When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed. 5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.
  • Page 88 Table 5.3 Command code and parameters (2 of 2) Command name IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK FLUSH CACHE Notes: Features Register CY: Cylinder Registers...

  • Page 89: Command Descriptions

    Interface Necessary to set parameters under the LBA mode. Not necessary to set parameters (The parameter is ignored if it is set.) May set parameters The device parameter is valid, and the head parameter is ignored. The command is addressed to the master device, but both the master device and the slave device execute it.
  • Page 90 CM: Command register DH: Device/Head register CH: Cylinder High register CL: Cylinder Low register SN: Sector Number register SC: Sector Count register Note: When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).
  • Page 91 Interface Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.
  • Page 92 The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

  • Page 93: Figure 5.2 Execution Example Of Read Multiple Command

    Interface Figure 5.2 Execution example of READ MULTIPLE command At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.
  • Page 94 (3) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. The data transfer starts at the timing of DMARQ signal assertion. The device controls the assertion or negation timing of the DMARQ signal. The device posts a status as the result of command execution only once at completion of the data transfer.
  • Page 95 Interface At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register. (4) READ VERIFY SECTOR(S) (X’40’...
  • Page 96 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
  • Page 97 Interface If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occured. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.
  • Page 98 (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
  • Page 99 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (7) WRITE DMA (X’CA’ or X’CB’) This command operates similarly to the WRITE SECTOR(S) command except for following events.
  • Page 100 A host system can select the following transfer mode using the SET FEATURES command. Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 4 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read)
  • Page 101 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
  • Page 102 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’ to X’F’) This command performs a seek operation to the track and selects the head specified in the command block registers.
  • Page 103 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (11) INITIALIZE DEVICE PARAMETERS (X’91’) The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command.
  • Page 104 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (12) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information (512 bytes) from the device.
  • Page 105 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 8) Word Value X’045A’...
  • Page 106 Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 8) Word Value 23-26 – Firmware revision (ASCII code, 8 characters, left) 27-46 Set by a device Model name (ASCII code, 40 characters, left) X’8010’ Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command X’0000’...
  • Page 107 Bit 1-0: Reserved *2 Word 1, 3, 6, 60-61 Word 01 Word 03 Word 06 Word 60-61 *3 Word 49: Capabilities Bit 15-14: Reserved 5-34 Description Valid = 0 MHJ2181AT MHK2120AT MHK2090AT X’3FFF’ X’3FFF’ X’3FFF’ X’10’ X’10’ X’10’ X’3F’ X’3F’ X’3F’...
  • Page 108 Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 8) Bit 13: Standby timer value. Factory default is 0. Bit 12: Reserved Bit 11: IORDY support Bit 10: IORDY inhibition Bit 9-0: Undefined Bit 9, 8: Always 1 *4 Word 51: PIO data transfer mode Bit 15-8: PIO data transfer mode...
  • Page 109 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 8) Bit 0 = 1 Mode 3 *9 WORD 80 Bit 15-6: Reserved Bit 5: ATA/ATAPI-5 supported = 1 Bit 4: ATA/ATAPI-4 supported = 1 Bit 3: ATA-3 supported = 1 Bit 2: ATA-2 supported = 1...
  • Page 110 Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 8) Bit 5: '1' = Supports the Power-Up In Standby set. Bit 4: '1' = Supports the Removable Media Status Notification feature Bit 3: '1' = Supports the Advanced Power Management feature set. Bit 2: '1' = Supports the CFA (Compact Flash Association) feature set.
  • Page 111 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (7 of 8) Bit 1 = '1': Mode 1 Bit 0 = '1': Mode 0 *15 WORD 93 Bits 15-14: Reserved Bit 13: '1' = CBLID- is a level higher than V '0' = CBLID- is a level lower than V Bits 12-8: In the case of Device 1 (slave drive), a valid value is set.
  • Page 112 Table 5.4 Information to be read by IDENTIFY DEVICE command (8 of 8) Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-6: Reserved Bit 5: 1: Enhanced security erase supported Bit 4: 1: Security counter expired Bit 3: 1: Security frozen Bit 2:...

  • Page 113: Table 5.5 Features Register Values And Settable Modes

    Interface (14) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. For the transfer mode (Feature register = 03), detail setting can be done using the Sector Count register.
  • Page 114 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) The host sets X’03’ to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.
  • Page 115 Interface Multiword DMA transfer mode X Ultra DMA transfer mode X The host writes the Sector Count register with the desired power management level and executes this command with the Features register X’05’, and then Advanced Power Management is enabled. Power management without standby Power management with standby Reserved...
  • Page 116 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.
  • Page 117 Interface Word 47 Bit 7-0 = 10: Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands. The READ MULTIPLE and WRITE MULTIPLE commands are Word 59 = 0000: disabled. The READ MULTIPLE and WRITE MULTIPLE commands are = 01xx: enabled.
  • Page 118 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (17) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.
  • Page 119 Interface At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked).

  • Page 120: Table 5.6 Diagnostic Code

    Table 5.6 Diagnostic code Code X’01’ X’03’ X’05’ X’8x’ attention: The device responds normally to this command without excuting internal diagnostic test. At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH)
  • Page 121 Interface (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
  • Page 122 (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
  • Page 123 Interface device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer. At command issuance (I/O registers setting contents) (CM) (DH) (CH)
  • Page 124 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 125 Interface Sector Count register value [X’00’] 1 to 3 [X’01’ to X’03’] 4 to 240 [X’04’ to X’F0’] 241 to 251 [X’F1’ to X’FB’] [X’FC’] [X’FD’] 254 to 255 [X’FE’ to X’FF’] attention: The automatic power-down is excuted if no command is coming for 30 min.
  • Page 126 (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function. At command issuance (I/O registers setting contents) (CM) (DH)
  • Page 127 Interface Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor. attention: The automatic power-down is excuted if no command is coming for 30 min.
  • Page 128 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode.
  • Page 129 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers.
  • Page 130 At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (29) SMART (X’B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.

  • Page 131: Table 5.7 Features Register Values (Subcommands) And Functions

    Interface Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 132 Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister X’D5’ SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.

  • Page 133: At Command Issuance (I/O Registers Setting Contents)

    Interface Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.

  • Page 134: 1F7 (St) Status Information

    At command completion (I-O registers setting contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h).

  • Page 135: Table 5.8 Format Of Device Attribute Value Data

    Interface Table 5.8 Format of device attribute value data Byte Data format version number Attribute 1 07 to 0C 0E to 169 Attribute 2 to attribute 30 Off-line data collection status Self test execution status 16C, 16D Off-line data collection execution time [sec.] Reserved Off-line data collection capability 170, 171...
  • Page 136 Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.
  • Page 137 Interface Current attribute value The current attribute value is the normalized raw attribute data. The value varies between 01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds.
  • Page 138 Self-test execution status Self-test has been completed normally or has not been executed. Self-test has been stopped by the host computer. Self-test has been suspended by hard or soft reset. Self-test has been aborted by a fatal error. Self-test has been completed abnormally by an unknown meaning.

  • Page 139: Table 5.10 Smart Error Log Data Format

    Interface Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. If an unrecoverable error is detected during execution of a command received by the device from the host computer, the device saves the SMART error log on the disk medium.
  • Page 140 Table 5.10 SMART error log data format (2/2) Byte Error log 1 Error data 46 to 58 5A, 5B 5C to 1C3 Error log 2 (The format of each error log is the same as Byte 02 to 5B.) Error log 5 1C4, 1C5 Number of unrecoverable errors that have occurred.

  • Page 141: Table 5.11 Smart Self Test Log Data Format

    Interface Status Unclear status Sleep status Standby status Active status or idle status (BSY bit = 0) Off-line data collection being executed 5 to F Reserved The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self test. When the self test is completed, the device saves the SMART self test log to the disk medium.
  • Page 142 (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.12 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

  • Page 143: Table 5.12 Contents Of Security Password

    Interface Table 5.12 Contents of security password Word 1 to 16 17 to 255 At command issuance (I-O register contents)) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE...
  • Page 144 At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (32) SECURITY ERASE UNIT (F4h) This command erases all user data. This command also invalidates the user password and releases the lock function.
  • Page 145 Interface At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (33) SECURITY FREEZE LOCK (F5h) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.
  • Page 146 READ DMA READ LONG READ MULTIPLE READ SECTORS At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) C141-E088-03EN WRITE DMA SECURITY DISABLE PASSWORD WRITE LONG SECURITY FREEZE LOCK WRITE MULTIPLE...

  • Page 147: Table 5.13 Contents Of Security Set Password Data

    Interface (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.13 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.
  • Page 148 At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH) (CL) (SN) (SC) (ER) (35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.12 to the device. Operation of the device varies as follows depending on whether the host specifies the master password.
  • Page 149 Interface LOCKED MODE conceled (in UNLOCK MODE) has no affect on the UNLOCK counter. Issuing this command in FROZEN MODE returns the Aborted Command error. At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents) (ST) (DH) (CH)

  • Page 150: Error Posting

    At command issuance (I-O register contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I-O register contents to be read) (ST) (DH) (CH) (CL) (SN) (SC) (ER) 5.3.3 Error posting Table 5.15 lists the defined errors that are valid for each command. Table 5.15 Command code and parameters (1 of 2) Command name READ SECTOR(S)
  • Page 151 Interface Table 5.15 Command code and parameters (2 of 2) Command name RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS READ NATIVE MAX ADDRESS EXECUTE DEVICE DIAGNOSTIC READ LONG WRITE LONG READ BUFFER WRITE BUFFER IDLE...

  • Page 152: Command Protocol

    5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1.

  • Page 153: Figure 5.3 Read Sector(S) Command Protocol

    Interface words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal.

  • Page 154: Data Transferring Commands From Host To Device

    device to 50 ms after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

  • Page 155: Figure 5.5 Write Sector(S) Command Protocol

    Interface a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers. b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register. c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

  • Page 156: Commands Without Data Transfer

    For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 s after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.

  • Page 157: Other Commands

    Interface Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issurance.

  • Page 158: Figure 5.7 Normal Dma Data Transfer

    When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. Figure 5.7 Normal DMA data transfer C141-E088-03EN 5.4 Command Protocol...

  • Page 159: Ultra Dma Feature Set

    Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only.

  • Page 160: Phases Of Operation

    Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command.

  • Page 161: Data Transfer Phase

    Interface g) Ultra DMA data in burst The device should not invert the state of this signal in the period from the moment of STOP signal negation or HDMARDY-signal assertion to the moment of inversion of the first STROBE signal. 5.5.2.2 Data transfer phase a) The Data transfer phase is defined as the period from The Ultra DMA burst initiation phase to Ultra DMA burst termination phase.

  • Page 162: Ultra Dma Data In Commands

    Once the transmitting side has outputted the ending request, the output state of STROBE signal should not be changed unless the receiving side has confirmed it. Then, if the STROBE signal is not in asserted state, The transmitting side should assert the STROBE signal. However, the assertion of the STROBE signal should not cause the data transfer to occur.

  • Page 163: The Data In Transfer

    Interface 9) The host shall negate STOP and assert HDMARDY- within t asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

  • Page 164: Terminating An Ultra Dma Data In Burst

    3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge. b) Host pausing an Ultra DMA data in burst 1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The host shall pause an Ultra DMA burst by negating HDMARDY-.
  • Page 165 Interface 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
  • Page 166 5) The host shall assert STOP no sooner than t HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated. 6) The device shall negate DMARQ within t STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

  • Page 167: Ultra Dma Data Out Commands

    Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.7 and 5.6.4.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

  • Page 168: Pausing An Ultra Dma Data Out Burst

    HSTROBE edge no more frequently than t Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t 3) The host shall not change the state of DD (15:0) until at least t generating an HSTROBE edge to latch the data. 4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.

  • Page 169: Terminating An Ultra Dma Data Out Burst

    Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.10 and 5.6.4.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
  • Page 170 b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

  • Page 171: Ultra Dma Crc Rules

    Interface 13) The host shall neither negate STOP nor HSTROBE until at least t negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

  • Page 172: Figure 5.8 An Example Of Generation Of Parallel Crc

    Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

  • Page 173: Series Termination Required For Ultra Dma

    Interface 5.5.6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device. Table 5.17 Recommended series termination for Ultra DMA Signal DIOR-:HDMARDY-:HSTROBE...

  • Page 174: Timing

    5.6 Timing 5.6.1 PIO data transfer Figure 5.10 shows of the data transfer timing between the device and the host system. C141-E088-03EN 5.6 Timing 5-101...

  • Page 175: Figure 5.10 Data Transfer Timing

    Interface Figure 5.10 Data transfer timing 5-102 C141-E088-03EN...

  • Page 176: Multiword Dma Data Transfer

    5.6.2 Multiword DMA data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. Delay time from DIOR-/DIOW- assertion to DMARQ negation Figure 5.11 Multiword DMA data transfer timing (mode 2) C141-E088-03EN 5.6 Timing 5-103...

  • Page 177: Transfer Of Ultra Dma Data

    Interface 5.6.3 Transfer of Ultra DMA data Figures 5.12 to 5.21 define the timings concerning every phase for the Ultra DMA Burst. Table 5.18 includes the timing for each Ultra DMA mode. 5.6.3.1 Starting of Ultra DMA data In Burst The timing for each Ultra DMA mode is included in 5.6.3.2.

  • Page 178: Ultra Dma Data Burst Timing Requirements

    5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) 2CYCTYP 2CYC IORDYZ C141-E088-03EN MODE 2 MODE 3 MODE 4 (in ns) (in ns) (in ns) MAX (see Notes 1 and 2) 5.6 Timing...
  • Page 179 Interface Table 5.18 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 (in ns) (in ns) ZIORDY Notes: 1) Unless otherwise specified, timing parameters shall be measured at the connector of th e sender or receiver to which the parameter applies (see Note 5 for exceptions).

  • Page 180: Sustained Ultra Dma Data In Burst

    5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

  • Page 181: Host Pausing An Ultra Dma Data In Burst

    Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t 2) If the t two more data words from the device.

  • Page 182: Device Terminating An Ultra Dma Data In Burst

    5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 183: Host Terminating An Ultra Dma Data In Burst

    Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 184: Initiating An Ultra Dma Data Out Burst

    5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.17 Initiating an Ultra DMA data out burst C141-E088-03EN 5.6 Timing...

  • Page 185: Sustained Ultra Dma Data Out Burst

    Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

  • Page 186: Device Pausing An Ultra Dma Data Out Burst

    5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t 2) If the t two more data words from the host.

  • Page 187: Host Terminating An Ultra Dma Data Out Burst

    Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 188: Figure 5.21 Device Terminating An Ultra Dma Data Out Burst

    5.6.3.11 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

  • Page 189: Power-On And Reset

    Interface 5.6.4 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Power-on Reset RESET – (2) Master and slave devices are present (2-drives configulation) Figure 5.22 Power on Reset Timing 5-116 PDIAG- negation C141-E088-03EN...

  • Page 190: Chapter 6 Operations

    CHAPTER 6 Operations Device Response to the Reset Address Translation Power Save Defect Management Read-Ahead Cache Write Cache C141-E088-03EN...

  • Page 191: Device Response To The Reset

    Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).

  • Page 192: Figure 6.1 Response To Power-On

    6.1 Device Response to the Reset 31 sec. 30 sec. Figure 6.1 Response to power-on C141-E088-03EN...

  • Page 193: Response To Hardware Reset

    Operations 6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal.

  • Page 194: Response To Software Reset

    6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully. After the slave device receives the software reset, the slave device shall report its presense and the result of the self-diagnostics to the master device as described below:...

  • Page 195: Response To Diagnostic Command

    Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.

  • Page 196: Address Translation

    (within the specified number of cylinders, heads, and sectors per track) in the current translation mode. The host can read an addressable parameter information from the device by the IDENTIFY DEVICE command (Words 54 to 56). C141-E088-03EN MHJ2181AT MHK2120AT MHK2090AT 16,383 16,383 8,455.20...

  • Page 197: Logical Address

    Operations 6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track that is specified by the INITIALIZE DEVICE PARAMETERS command.

  • Page 198: Power Save

    (2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. If the last sector of a physical track is used, the track is switched and the next LBA is assigned to the initial sector of the subsequent physical track.
  • Page 199 Operations The drive moves from the Active mode to the idle mode by itself. Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed.

  • Page 200: Power Commands

    When one of following commands is issued, the command is executed normally and the device is still stayed in the standby mode. Reset (hardware or software) STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command (4) Sleep mode The power consumption of the drive is minimal in this mode.

  • Page 201: Spare Area

    Operations 6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (4 cylinders) 2) Spare cylinder for alternative assignment: used for automatic alternative assignment at read error occurrence. (4 cylinders) 6.4.2 Alternating defective sectors The two alternating methods described below are available:...

  • Page 202: Figure 6.8 Alternate Cylinder Assignment

    (2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0.

  • Page 203: Read-Ahead Cache

    Operations An unrecoverable write error occurs during write error retry, automatic alternate assignment is performed. 6.5 Read-Ahead Cache After read command which involes read data from the disk medium is completed, the read-ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer.
  • Page 204 READ SECTOR (S) READ MULTIPLE READ DMA When caching operation is disabled by the SET FEATURES command, no caching operation is performed. (2) Data that are object of caching operation Follow data are object of caching operation. 1) Read-ahead data read from the medium to the data buffer after completion of the command that are object of caching operation.

  • Page 205: Usage Of Read Segment

    Operations READ MULTIPLE WRITE SECTOR(S) WRITE MULTIPLE WRITE VERIFY SECTOR(S) 3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error. 5) Soft reset or hard reset occurs, or power is turned off. 6) The device enters the sleep mode.

  • Page 206: Sequential Read

    2) Transfers the requested data that already read to the host system with reading the requested data from the disk media. Read-requested data 3) After reading the requested data and transferring the requested data to the host system had been completed, the disk drive stops command execution without performing the read-ahead operation.
  • Page 207 Operations 1) At receiving the sequential read command, the disk drive sets the DAP and HAP to the start address of the segment and reads the requested data from the load of the segment. Mis-hit data 2) The disk drive transfers the requested data that is already read to the host system with reading the requested data.
  • Page 208 b. Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system. The disk drive performs the read-ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system.

  • Page 209: Full Hit (Hit All)

    Operations 4) Finally, the cache data in the buffer is as follows. Start LBA Non-sequential command immediately after sequential command When a sequential read command (first read) has been executed, the first read operation should be stopped if a non-sequential read command has been received and then, ten or more of the non-sequential read commands have been received.

  • Page 210: Partially Hit

    3) The cache data for next read command is as follows. Start LBA 6.5.3.4 Partially hit A part of requested data including a lead sector are stored in the data buffer. The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data, and reads remaining requested data from the disk media directly.

  • Page 211: Write Cache

    Operations 3) The cache data for next read command is as follows. Start LBA 6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed.
  • Page 212 The drive uses a cache data of the last write command as a read cache data. When a read command is issued to the same address after the write command (cache hit), the read operation to the disk medium is not performed. If an error occurs during the write operation, the device retries the processing.
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  • Page 214: Glossary

    Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
  • Page 215 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
  • Page 216 Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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  • Page 218: Acronyms And Abbreviations

    Acronyms and Abbreviations ABRT Abored command Automatic idle control AMNF Address mark not found AT attachment American wire gage Bad block detected BIOS Basic input-output system CORR Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start/stop Cylinder register dB A-scale weighting...
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  • Page 220 1-drive connection 2-4 2-drive connection 2-4 16/17 MTR MEEPRML 4-10 16/17 MTR MEEPRM 4-13 Acceleration mode 4-21 Acoustic noise 1-7 Acoustic noise specification 1-8 Active mode 6-10 Actuator 2-3, 4-3 Actuator motor control 4-19 Adaptability 1-2 Adaptive equalizer circuit 4-12 ADC 4-17 A/D converter 4-17 Address translation 6-7, 6-8...
  • Page 221 Index Data transferring command 5-79, 5-81 Data transfer timing 5-102 DE 2-3 Default parameter 6-7 Defect management 6-11 Device configuration 2-1 Device connection 3-10 Device connector 3-9 Device Control register 5-13 Device/Head register 5-10 Device overview 1-1 Device response to reset 6-2 DF 5-12 Diagnostic code 5-9 Dimension 3-2, 3-3...
  • Page 222 Mean time to repair 1-9 Media defect 1-10 Microprocessor unit 4-14 Mis-hit 6-16 Model and product number 1-5 Model name and product number 1-5 Mounting 3-4 Move head to reference cylinder 4-15 MPU 4-14 MTBF 1-9 MTTR 1-9 Multiword DMA data transfer timing 5-103 Multiword mode 2 2-4 NIEN 5-13 No hit 6-16...
  • Page 223 Index Servo B 4-19 Servo burst capture 4-17 Servo burst capture circuit 4-17 Servo C 4-19 Servo circuit 4-4 Servo control 4-14 Servo control circuit 4-14 Servo D 4-19 Servo format, data-surface 4-18 Servo frame format 4-18 Servo mark 4-19 SET FEATURES 5-40 SET MULTIPLE MODE 5-42 Shock 1-8...
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  • Page 225 We would appreciate your comments and suggestions regarding this manual. Manual code C141-E088-03EN Manual name MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance Technical level Organization Clarity Accuracy Comments & Suggestions List any errors or suggestions for improvement.
  • Page 226 MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES PRODUCT MANUAL MHJ2181AT, MHK2120AT, MHK2090AT, MHK2060AT DISK DRIVES PRODUCT MANUAL C141-E088-03EN C141-E088-03EN...

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