Timer 1 Control Register (T1Con) - Samsung S3F80P5X User Manual

S3F80P5_UM_ REV1.00

TIMER 1 CONTROL REGISTER (T1CON)

The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable. T1CON
contains control settings for the following T1 functions:
— Timer 1 input clock selection
— Timer 1 operating mode selection
— Timer 1 16-bit down counter clear
— Timer 1 overflow interrupt enable/disable
— Timer 1 match or capture interrupt enable/disable
— Timer 1 interrupt pending control (read for status, write to clear)
A reset operation clears T1CON to '00H', selecting fosc divided by 4 as the T1 clock, configuring Timer 1 as a
normal interval Timer, and disabling the Timer 1 interrupts.
MSB
Timer 1 Input Clock Selection Bits:
00 = f /4
OSC
01 = f /8
OSC
10 = f /16
OSC
11 = Internal clock (T-F/F)
Timer 1 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = Capture mode (capture on rising and
falling edge, counter running, OVF can occur)
Timer 1 Control Register (T1CON)
FAH, Set 1, Bank 0 , R/W
.7 .6 .5 .4
Figure 11-4. Timer 1 Control Register (T1CON)
.3 .2 .1 .0
Timer 1 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 1 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 1 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
LSB
TIMER 1
11-5