Sed&R (Stop Error Detect And Recovery) - Samsung S3F80P5X User Manual

S3F80P5_UM_ REV1.00
SED&R (Stop Error Detect and Recovery)
The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that
can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0. One is
releasing from stop status by switching the level of input port (P0) and the other is keeping the chip from entering
stop mode when the chip is in abnormal status.
— Releasing from stop mode
When RESET Control Bit is set to '0' (smart option @ 03FH), if falling edge input signal enters in through
Port0, S3F80P5 is released from stop mode and generates reset signal. On the other hand, when RESET
Control Bit is set to '1' (smart option @ 03FH), S3F80P5 is only released stop mode, reset doesn't occur.
When the falling edge of a pin on Port0 is entered, the chip is released from stop mode even though external
interrupt is disabled.
— Keeping the chip from entering abnormal - stop mode
This circuit detects the abnormal status by checking the port (P0) status. If the chip is in abnormal status it
keeps from entering stop mode.
In case of P2.0, SED&R circuit isn't implemented. So although 1pins, P2.0, have the falling edge input signal in
stop mode, if external interrupt is disabled, the stop state of S3F80P5 is unchanged. Do not use stop mode if you
are using an external clock source because Xin input must be cleared internally to VSS to reduce current
leakage.
NOTE
RESET
8-13