Peripheral Interrupt Control Registers - Samsung S3F80P5X User Manual

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by that peripheral (See Table 5-3).
Interrupt Source
Timer 0 match/capture or
Timer 0 overflow
Timer 1 match/capture or
Timer 1 overflow
Counter A
Timer 2 match/capture or
Timer 2 overflow
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P2.0 external interrupt
NOTES:
1. Because the timer 0, timer1 and timer 2 overflow interrupts are cleared by hardware, the T0CON, T1CON and
T2CON registers control only the enable/disable functions. The T0CON, T1CON and T2CON registers contain
enable/disable and pending bits for the timer 0, timer1 and timer2 match/capture interrupts, respectively.
2. If a interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.
5-8
Table 5-3. Vectored Interrupt Source Control and Data Registers
Interrupt Level
IRQ0
IRQ1
IRQ2
IRQ3
IRQ7
IRQ6
IRQ4
Register(s)
T0CON (see Note)
T0DATA
T1CON (see Note)
T1DATAH, T1DATAL
CACON
CADATAH, CADATAL
T2CON (see Note)
T2DATAH, T2DATAL
P0CONH
P0INT
P0PND
P0CONL
P0INT
P0PND
P2CONL
P2INT
P2PND
S3F80P5_UM_ REV1.00
Location(s) in Set 1
D2H
D1H
FAH
F8H, F9H
F3H
F4H, F5H
E8H
E6H, E7H
E8H
F1H
F2H
E9H
F1H
F2H
EDH
E5H
E6H
Bank
Bank0
Bank0
Bank0
Bank1
Bank0
Bank0
Bank0