Epson L-1000 Technical Manual page 171

APPENDIX
Refer to Figures A-3 through A-5 for CPU timing diagrams.
Three oscillations define one state. The OP code fetch requires four states; during Tl to T3, program memory
is read; instructions are interpreted during T4. Address bus lines 15-8 are output from Tl to T4. Address bus
lines 7-0 (PD7-0) are used in the multiplex mode; the address is latched during T1 at the ALE signal. Since
the memory addressed is enabled after disengaging the driver (AD7-0), RD is output from T1-T3, fetched at
T3, and processed internally at T4. The ALE and RD signals are executed from T1-T3; the OP code fetch
for these two signals is performed at T4. The WR signal is output from the middle of T1 to the beginning of
T3. The address and ALE timing is the same as that for memory read; however following address output AD7-0
(PD7-0) are not disabled, and write data is output at AD7-0 at the beginning of T1 and the end of T3.
NOTE:
When PD7-0 are set to the multiplexed address/data bus (AD7-0) and PF7-0 to the address bus (AB7-0),
the RD and WR signals in the machine cycle are HIGH when memory is not being accessed.
A-6
Figure A-5. Memory Write Timing
REV.-A
LQ-500/ L-1000