HP XM600 - Kayak - 128 MB RAM Technical Reference Manual page 46

2 System Board
Memory Controller Hub (MCH) 82820
A maximum number of 32 Rambus devices (128 Mbit technology implies 512
MB maximum in 16 MB increments, 256 Mbit technology implies 1 GB
maximum in 32 MB increments) are supported on the Direct Rambus
channel without external logic.
The MCH also provides optional data integrity features including ECC in the
memory array. During DRAM writes, ECC is generated on a QWord (64 bit)
basis. During DRAM reads, the MCH supports multiple-bit error detection
and single-bit error correction when the ECC mode is enabled.
MCH will scrub single bit errors by writing the corrected value back into
DRAM for all reads when hardware scrubbing is enabled. This, however,
does not include reads launched in order to satisfy an AGP aperture
translation.
ECC can only be enabled when all RDRAM devices are populated in a system
that supports the extra two data bits used to store the ECC code.
Rambus Channel
The single Direct Rambus Channel is a 16-bit wide bidirectional
bus—commands and data can be transferred in both directions
simultaneously. The Rambus Channel is connected to the memory module
slots and to the MCH chip.
The channel runs at 300 or 400 MHz and supports up to 32 Rambus devices
(individual chips). The maximum available data bandwidth is 1.6GB/sec at
400 MHz.
RIMM Memory Slots
The HP Kayak XM600 Series 2 has two RIMM memory sockets, RIMM0
RIMM1
and RIMM1, available for installing RDRAM memory modules.
RIMM0
If only one RDRAM module is being used, it must be inserted in RIMM0
(the socket nearest the processor). A Continuity module must be inserted
in the RIMM1 socket.
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