Main Memory Controller - HP XM600 - Kayak - 128 MB RAM Technical Reference Manual

AGP PCI Bus
Implementation
AGP 1X with pipelining, sideband addressing can be added: uses 66 MHz,
•
32-bits, 3.3 V, increased bus efficiency, 266 MB/s peak transfer rate.
AGP 2X with pipelining, sideband addressing can be added: 66 MHz
•
double clocked, 32-bits, 3.3 V, increased bus efficiency, 533 MB/s peak
transfer rate.
AGP 4X with pipelining, sideband addressing can be added: 133 MHz quad
•
clocked, 32-bits, 1.5 V, increased bus efficiency, 1066 MB/s peak transfer
rate
AGP 4x Bus
(133 MHz)
AGP
Connector

Main Memory Controller

The main memory controller is integrated in the MCH supporting a single
Direct Rambus channel.
DRAM Interface
The MCH provides optional Host bus error checking for data, address,
request and response signals. 300 MHz, 356 MHz and 400 MHz Direct
Rambus devices are supported in any of 64, 128 or 256 Mbit technology.
64 and 128 Mbit RDRAMs use page sizes of 1 kbyte, while 256 Mb devices
target 1 kbyte or 2 kbyte pages.
GX-Device 1
AGP Port
Interface
2 System Board
Memory Controller Hub (MCH) 82820
Pentium III Processor
820
Memory
Controller Hub
(MCH)
82820
I/O Controller Hub
(ICH) 82801AA
45