Hp_Processorcachememory - HP Integrity rx7620 Datasheet

Table 3-5
Class: HP_HardwareThread
Property name
OperationalStatus
StatusDescriptions
HealthState
CIM_LogicalElement
CIM_EnabledLogicalElement
EnabledState
RequestedState
EnabledDefault
CIM_HardwareThread
InstanceID
HP_HardwareThread

HP_ProcessorCacheMemory

3-3-5
HP_ProcessorCacheMemory implements the class HP_CacheMemory which extends CIM_Memory to
model the processor caches.
The following properties are implemented.
Property implementation
•
0 (Unknown)
•
2 (OK), when CPU is enabled and operational
•
5 (Predictive Failure), when IML error information is
logged for this CPU
•
6 (Error), when CPU is disabled through POST
error
•
10 (Stopped), when CPU is disabled through RBSU
StatusDescriptions[0] text per OperationalStatus[0]:
•
Processor-module status unknown.
•
Processor-module status OK
•
Processor-module is degraded, it is predicted to Fail
•
Processor-module in Slot: a Socket: b disabled by
BIOS (POST Error), where a is the slot number and
b is the socket number
•
Processor-module in Slot: a Socket: b disabled by
User through BIOS Setup, where a is the slot
number and b is the socket number
•
0 (Unknown), when OperationalStatus[0]=0
(Unknown)
•
5 (OK), when OperationalStatus[0]=2 (OK)
•
15 (Minor Failure), when OperationalStatus[0]=10
(Stopped)
•
20 (Major Failure), when OperationalStatus[0]=5
(Predictive Failure)
•
25 (Critical Failure), when OperationalStatus[0]=6
(Error)
2 (Enabled)
12 (Not Applicable)
2 (Enabled)
HPQ:HP_HardwareThread:n, where n is a unique,
sequentially-assigned number in the form 001, 002,
and so on.
2BCPU 31