Fixed I/O Map; I/O Map - Intel D845GEBV2 - OCTOBRE 2002 Manual

Intel Desktop Board D845GEBV2/D845GERG2 Technical Product Specification

2.3 Fixed I/O Map

Table 20.

I/O Map

Address (hex)
0000 - 00FF
0170 - 0177
01F0 - 01F7
(Note 1)
0228 - 022F
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0376
0377, bits 6:0
0378 - 037F
03B0 - 03BB
03C0 - 03DF
03E8 - 03EF
03F0 - 03F5
03F6
03F8 - 03FF
04D0 - 04D1
LPTn + 400
(Note 2)
0CF8 - 0CFB
(Note 3)
0CF9
0CFC - 0CFF
FFA0 - FFA7
FFA8 - FFAF
Notes:
1. Default, but can be changed to another address range
2. Dword access only
3. Byte access only
✏
NOTE
Some additional I/O addresses are not available due to ICH4 address aliassing. The ICH4 data
sheet provides more information on address aliassing.
For information about
Obtaining the ICH4 data sheet
54
Size Description
256 bytes Used by the Desktop Board D845GEBV2/D845GERG2.
Refer to the ICH4 data sheet for dynamic addressing
information.
8 bytes Secondary IDE channel
8 bytes Primary IDE channel
8 bytes LPT3
8 bytes LPT2
8 bytes COM4
8 bytes COM2
1 byte Secondary IDE channel command port
7 bits Secondary IDE channel status port
8 bytes LPT1
12 bytes Intel 82845GE GMCH
32 bytes Intel 82845GE GMCH
8 bytes COM3
6 bytes Diskette channel 1
1 byte Primary IDE channel command port
8 bytes COM1
2 bytes Edge/level triggered PIC
8 bytes ECP port, LPTn base address + 400h
4 bytes PCI configuration address register
1 byte Turbo and reset control register
4 bytes PCI configuration data register
8 bytes Primary bus master IDE registers
8 bytes Secondary bus master IDE registers
Refer to
Section 1.3 on page 19