Fixed I/O Map; I/O Map - Intel DG965MQ Specification

Intel Desktop Board DG965MQ Technical Product Specification
2.3

Fixed I/O Map

Table 14. I/O Map
Address (hex)
0000 - 00FF
01F0 - 01F7
(Note 1)
0228 - 022F
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0378 - 037F
03B0 - 03BB
03C0 - 03DF
03E8 - 03EF
03F0 - 03F5
03F4 - 03F7
03F8 - 03FF
04D0 - 04D1
LPTn + 400
(Note 2)
0CF8 - 0CFB
(Note 3)
0CF9
0CFC - 0CFF
FFA0 - FFA7
Notes:
1. Default, but can be changed to another address range
2. Dword access only
3. Byte access only
NOTE
Some additional I/O addresses are not available due to ICH8 address aliasing. The
ICH8 data sheet provides more information on address aliasing.
For information about
Obtaining the ICH8 data sheet
46
Size Description
256 bytes Used by the Desktop Board DG965MQ. Refer to the ICH8
data sheet for dynamic addressing information.
8 bytes Primary Parallel ATE IDE channel command block
8 bytes LPT3
8 bytes LPT2
8 bytes COM4
8 bytes COM2
8 bytes LPT1
12 bytes Intel 82G965 GMCH
32 bytes Intel 82G965 GMCH
8 bytes COM3
6 bytes Diskette channel
4 bytes Primary Parallel ATA IDE channel control block
8 bytes COM1
2 bytes Edge/level triggered PIC
8 bytes ECP port, LPTn base address + 400h
4 bytes PCI configuration address register
1 byte Reset control register
4 bytes PCI configuration data register
8 bytes Primary Parallel ATA IDE bus master registers
Refer to
Section 1.2 on page 15