Power Management Setup - JETWAY 993BSR4A User Manual

This section describes features of the VIA Apollo Pro-Plus AGPset. If your system contains a
different chipset, this section will bear little resemblance to what you see on your screen.
ADVANCED OPTIONS. The parameters in this screen are for system designers, service
personnel, and technically competent users only. Do not reset these values unless you
understand the consequences of your changes.
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
Read Around write
Concurrent PCI/Host
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-2X Mode
OnChip USB
U S B K e yboard S u pport
E s c : Q u it
F 1 : H e lp P U / P D / + / - : M odify
F 5 : O l d V a lues ( S h ift) F 2 : Color
• In this item you can choose the CPU HOST/PCI Clock. The setting are:
Default ,66/33,75/37,83/41,100/33,103/34, 112/37,124/41,105/35,110/36,115/38,120/40,
133/44.
When the setting is :"default" the CPU HOST Clock will depend on the setting of JP9.
If JP9 are set to 66MHz only have the choice of 66/33, 75/37, 83/41 on screen.
If the JP9 are setting at 100MHz, then you can have 100/33,103/34,112/37,124/41,105/35,
110/36,115/38,120/40,133/44.
*Please turn off system power if the screen does not have any display after change of the
setting. Then press and hold down " INS " key, and turn on system power again (release
" INS " key till the screen has display) to reset correct frequency of CPU HOST clock.
•
DRAM Clock: In this item you have the choice : Host CLK , HCLK –33M. We recommend
the Max.

3-4 POWER MANAGEMENT SETUP

ROM PCI/ISA BIOS (2A6LGJ1F)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: SDRAM 10ns
: SDRAM 10ns
: 3
: Host CLK
: Disabled
: Disabled
: Disabled
: Enabled
: Enabled
: 64M
: Enabled
: Enabled
: D i sabled
¡ ô ¡ õ ¡ ÷ ¡ ö : S e lect Item
A u to D e tect D I MM/PCI Clk : E n abled
S p read S p ectrum
CP U H o st/PCI Clock
F 6 : L o ad O p timal D e faults
F 7 : L o ad S t andard D e faults
Figure 3-3
18
: D i sabled
: D e fault