Pci Timing Settings; Hypertransport Settings - JETWAY 939AGPECR110 User Manual

3-6-3 PCI Timing Settings

PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to PCI Post Write
PCI Delay Transaction
VLink Data Rate
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.

3-6-4 Hypertransport Settings

Hypertransport Link Frequency
Hypertransport Link Width In
Hypertransport Link Width Out
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Disabled
Disabled
Enabled
Disabled
8X
F6:Optimized Defaults
Phoenix – AwardBIOS CMOS Setup Utility
Hypertransport Settings
1 GHz
16 bit
16 bit
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
Menu Level >>
F7:Standard Defaults
27
Item Help
F1:General Help
Item Help
F1:General Help