Pci Timing Settings; Integrated Peripherals - JETWAY PT88BSPRO User Manual

3-6-3 PCI Timing Settings

PCI Master 0 WS Write
PCI Delay Transaction
Vlink Mode Selection
Vlink 8X Support
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.

3-7 Integrated Peripherals

> Onboard IDE Function
> Onboard Device Function
> Onboard Super IO Function
Init Display First
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
Onboard IDE Function
Please refer to section 3-7-1
Onboard Device Function
Please refer to section 3-7-2
Onboard Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings are:
PCI Slot, AGP Slot.
Phoenix – AwardBIOS CMOS Setup Utility
PCI Timing Settings
Enabled
Enabled
By Auto
Enabled
F6:Optimized Defaults
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
37
Item Help
Menu Level >>
F7:Standard Defaults
Item Help
Menu Level >>
F7:Standard Defaults