Dram Timing Settings; Agp Function Settings; Agp Timing Settings - JETWAY 939AGPECR110 User Manual

3-6-1 DRAM Timing Settings

Auto Configuration
x DRAM CAS Latency
x RAS Active Time
x RAS to CAS Delay
x RAS Precharge Time
x DRAM Bank Interleaving
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.

3-6-2 AGP Timing Settings

AGP Aperture Size
AGP Transfer Mode
AGP Driving Control
X AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
AGP 3.0 Calibration Cycle
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Auto
CL=2.5
8T
4T
4T
Enabled
F6:Optimized Defaults
Phoenix – AwardBIOS CMOS Setup Utility
AGP Timing Settings
128M
8X
Auto
AA
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
Menu Level >>
F7:Standard Defaults
26
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