Nmi (I); Own# (I/O); Pmi# (I); Pwrgood (I) - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Signals Reference
A.1.46

NMI (I)

The NMI signal is the Non-maskable Interrupt signal. Asserting NMI causes an interrupt
with an internally supplied vector value of 2. An external interrupt-acknowledge
transaction is not generated. If NMI is asserted during the execution of an NMI service
routine, it remains pending and is recognized after the EOI is executed by the NMI
service routine. At most, one assertion of NMI is held pending.
NMI is rising-edge sensitive. Recognition of NMI is guaranteed in a specific clock if it is
asserted synchronously and meets the setup and hold times. If asserted
asynchronously, asserted and deasserted pulse widths of NMI must be a minimum of
two clocks.This signal must be software configured to be used either as NMI or as
another local interrupt (LINT1 pin).
A.1.47

OWN# (I/O)

The Guaranteed Cache Line Ownership (OWN#) signal is driven to the bus on the
second clock of the Request Phase on the Ab[5]# pin. OWN# is asserted if cache line
ownership is guaranteed. This allows a memory controller to ignore memory updates
due to implicit writebacks.
A.1.48

PMI# (I)

The Platform Management Interrupt (PMI#) signal triggers the highest priority
interrupt to the processor. PMI# is usually used by the system to trigger system events
that will be handled by platform specific firmware.
A.1.49

PWRGOOD (I)

The Power Good (PWRGOOD) signal must be deasserted (L) during power-on, and must
be asserted (H) after RESET# is first asserted by the system.
A.1.50

REQ[5:0]# (I/O)

The REQ[5:0]# are the Request Command signals. They are asserted by the current
bus owner in both clocks of the Request Phase. In the first clock, the REQa[5:0]#
signals define the transaction type to a level of detail that is sufficient to begin a snoop
request. In the second clock, REQb[5:0]# signals carry additional information to define
the complete transaction type. REQb[4:3]# signals transmit DSZ[1:0]# or the data
transfer information of the requestor for transactions that involve data transfer.
REQb[2:0]# signals transmit LEN[2:0]# (the data transfer length information). In both
clocks, REQ[5:0]# and ADS# are protected by parity RP#.
All receiving agents observe the REQ[5:0]# signals to determine the transaction type
and participate in the transaction as necessary, as shown in
® ®
Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Table A-10.
101