Ccl# (I/O); Cpupres# (O); D[127:0]# (I/O); D/C# (I/O) - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

A symmetric agent can deassert BREQn# before it becomes a symmetric owner. A
symmetric agent can reassert BREQn# after keeping it deasserted for one clock.
A.1.16

CCL# (I/O)

CCL# is the Cache Cleanse signal. It is driven on the second clock of the Request Phase
on the EXF[2]#/Ab[5]# pin. CCL# is asserted for Memory Write transaction to indicate
that a modified line in a processor may be written to memory without being invalidated
in its caches.
A.1.17

CPUPRES# (O)

CPUPRES# can be used to detect the presence of a processor in a socket. A ground
indicates that a processor is installed, while an open indicates that a processor is not
installed.
A.1.18

D[127:0]# (I/O)

The Data (D[127:0]#) signals provide a 128-bit data path between various system bus
agents. Partial transfers require one data transfer clock with valid data on the byte(s)
indicated by asserted byte enables BE[7:0]# and A[3]#. Data signals that are not valid
for a particular transfer must still have correct ECC (if data bus error checking is
enabled). The data driver asserts DRDY# to indicate a valid data transfer.
A.1.19

D/C# (I/O)

The Data/Code (D/C#) signal is used to indicate data (1) or code (0) on REQa[1]#,
only during Memory Read transactions.
A.1.20

DBSY# (I/O)

The Data Bus Busy (DBSY#) signal is asserted by the agent that is responsible for
driving data on the system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted.
DBSY# is replicated three times to enable partitioning of the data paths in the system
agents. This copy of the Data Bus Busy signal (DBSY#) is an input as well as an output.
A.1.21

DBSY_C1# (O)

DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal
(DBSY_C1#) is an output only.
A.1.22

DBSY_C2# (O)

DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal
(DBSY_C2#) is an output only.
A.1.23

DEFER# (I)

The DEFER# signal is asserted by an agent to indicate that the transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of
the priority agent.
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Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet
Signals Reference