Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual page 84

Table 6-4. Processor Information ROM Format (Sheet 3 of 3)
Offset/
Section
3Ch
3Dh
Part Numbers
3Eh
45h
4Dh
62h
Thermal Reference
63h
64h
65h
66h
Features
67h
6Bh
73h
77h
78h
79h
Other
7Ah
84
# of
Function
Bits
8 Reserved
8 Checksum
56 Processor Part Number
64 Processor Electronic
Signature
168 Reserved
8 Checksum
8 Upper Temp Reference Byte
8 Thermal Calibration Offset
Byte Present
8 Reserved
8 Checksum
32 IA-32 Processor Core
Feature Flags
64 Reserved
32 Processor Feature Flags
4 Number of Devices in TAP
Chain
4 Reserved
8 Checksum
16 Reserved
Dual-Core Intel
System Management Feature Specifications
Notes
Reserved for future use
1 byte checksum
Seven 8-bit ASCII characters
64-bit identification number
Reserved for future use
1 byte checksum
Hex value of thermal upper temp
limit
Number of degrees in error (±)
Reserved for future use
1 byte checksum
From 32 bit CPUID
Reserved (Processor core feature
flags implemented in the
®
Itanium processor family)
All others are reserved:
[9] = Demand Based Switching
Enabled
[8] = Core Level Lockstep
Enabled
[7] = Socket Level Lockstep
Enabled
[6] = Dual Core Enabled
[5] = Hyper-Threading Enabled
[4] = Upper temp reference byte
[3] = Thermal calibration offset
byte present
[2] = Scratch EERPOM present
[1] = Core VID Present
One 4-bit hex digit
Reserved for future use
1 byte checksum
Reserved for future use
® ®
Itanium Processor 9000 and 9100 Series Datasheet
Examples
00h
Add up by byte and take
2's complement
80549KC
• 3Eh = "8"
• 3Fh = "0"
• 40h = "5"
• 41h = "4"
• 42h = "2"
• 43h = "K"
• 44h = "C"
May have padded zeros
x0h
Add up by byte and take
2's complement
Default = 92 = 5Ch
will be set per
part and expected to be
~ +12C
00h
Add up by byte and take
2's complement.
4387FBFFh
0000 0000 6380 811Bh
1 indicates EEPROM data
for specified field is valid.
2h for dual-core
processor
0h
Add up by byte and take
2's complement.
0000h