Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual page 7

A-1 Address Space Size ........................................................................................... 92
A-2 Effective Memory Type Signal Encoding ................................................................ 92
A-3 Special Transaction Encoding on Byte Enables ....................................................... 93
A-5 BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect ...................... 95
A-4 BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect ...................... 95
A-6 BR[3:0]# Signals and Agent IDs ......................................................................... 95
A-7 DID[9:0]# Encoding .......................................................................................... 97
A-8 Extended Function Signals .................................................................................. 98
A-9 Length of Data Transfers .................................................................................. 100
A-10 Transaction Types Defined by REQa#/REQb# Signals ........................................... 102
A-11 STBp[7:0]# and STBn[7:0]# Associations .......................................................... 104
A-12 Output Signals ................................................................................................ 105
A-13 Input Signals .................................................................................................. 105
A-14 Input/Output Signals (Single Driver) .................................................................. 106
A-15 Input/Output Signals (Multiple Driver)................................................................ 107
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Dual-Core Intel Itanium Processor 9000 and 9100 Series Datasheet 7