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Super X13DGU User's Manual
CPU1-D1/D2
CPU1-C1/C2
CPU1-B1/B2
CPU1-H1/H2
CPU1-G1/G2
CPU1-F1/F2
MCIO x8
VERT
MCIO x8
VERT
MCIO x8
PCI-E GEN5 X8
VERT
MCIO x8
PCI-E GEN5 X8
VERT
PCI-E GEN5 X8
PCI-E GEN5 X16
MCIO x8
VERT
JMCIO27/28
PCI-E GEN5 X16
MCIO x8
VERT
JMCIO25/26
PCI-E GEN5 X16
MCIO x8
RA
JMCIO11/12
MCIO x8
PCIe Gen5
PCI-E GEN5 x4x4
Host0
RA
Host1
Switch
JMCIO9
MCIO x8
PCI-E GEN5 x4x4
Host0
RA
Host1
JMCIO10
PCI-E GEN5 X16
MCIO x8
RA
JMCIO23/24
PCI-E GEN5 X16
MCIO x8
VERT
JMCIO21/22
PCI-E GEN5 X16
MCIO x8
VERT
JMCIO17/18
Dedicated LAN PHY
Note: This is a generic block diagram and may not exactly represent the features on
your motherboard. See the previous pages for the actual specifications of your moth-
erboard.
X13DGU
CPU1-A1/A2
P0
UPI
P1
CPU1
CPU1-E1/E2
UPI
P2
UPI
P3
UPI
Intel
RJ45
10G LAN
X710
RJ45
PCI-E GEN5 X16
DMI x4
Host 0
DMI3
Host 1
PCH
X710 NC-SI
JNCSI Header
BMC F/W
BMC
VGA Port
AST2600
COM Port
DDR4
System Block Diagram
CPU2-A1/A2
CPU2-B1/B2
P1
P0
CPU2
CPU2-E1/E2
CPU2-F1/F2
P2
P3
MCIO x8
VERT
MCIO x8
VERT
MCIO x8
PCIE GEN5 X8
VERT
MCIO x8
PCIE GEN5 X8
VERT
From PCH
PCI-E GEN5 X16
#2
#1
USB 2.0
Host0
USB
PCIe Gen5
header
#2
Switch
#1
USB 3.0
USB
Host1
rear IO
SATA0-11
TPM HEADER
PCI-E GEN5 X16
Debug Card
TPM
CPLD
LCMXO3LF
-6900C
eMMC
BIOS
18
CPU2-C1/C2
CPU2-D1/D2
CPU2-G1/G2
CPU2-H1/H2
PCIE GEN5 X4
M.2A
PCIE GEN5 X4
PCIe GEN5
JM2_HC1
Mux
SATA3 x2
M.2B
SATA3 x2
JM2_HC2
Hybrid M.2s
MCIO x8
VERT
JMCIO35/36
PCI-E GEN5 X16
MCIO x8
Vert
JMCIO33/34
PCI-E GEN5 X16
MCIO x8
RA
JMCIO15/16
PCI-E GEN5 x4x4
MCIO x8
Host0
RA
Host1
JMCIO14
PCI-E GEN5 x4x4
MCIO x8
Host0
RA
Host1
JMCIO13
PCI-E GEN5 X16
MCIO x8
RA
JMCIO31/32
MCIO x8
VERT
PCI-E GEN5 X16
JMCIO29/30
MCIO x8
VERT
JMCIO19/20
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