Table of Contents
Advertisement
Chapter 4: UEFI BIOS
return the modified data. However, it may be the case that a line "reads" in an A state,
and all the snoops come back with a "miss". This can happen if another socket reads the
line earlier and then has silently dropped it from its cache without modifying it. If "Stale
AtoS" is enabled, a line will transition to the S state when the line in the A state returns
only snoop misses. That way, subsequent reads to the line will encounter it in the S state
and will not have to snoop, saving the latency and snoop bandwidth. Stale "AtoS" may
be beneficial in a workload where there are many cross-socket reads. The options are
Disable, Enable, and Auto.
LLC Dead Line Alloc
Select Enable to opportunistically fill the deadlines in the LLC. The options are Disable,
Enable, and Auto.
Memory Configuration
This feature allows you to configure the Integrated Memory Controller (iMC) settings.
Enforce DDR Memory Frequency POR
Select POR to enforce Plan of Record (POR) restrictions for DDR memory frequency
and voltage programming. The options are POR and Disable.
Memory Frequency
Use this feature to set the maximum memory frequency for onboard memory modules.
The options are Auto, 3200, 3600, 4000, 4400, 4800, 5200, and 5600. (Please note that
the available options are CPU-dependent.)
Data Scrambling for DDR5
Select Enable to enable data scrambling for DDR5 modules to enhance memory data
security. The options are Disable and Enable.
Enable ADR (Available when "Enable fADR" is set to Disable)
Select Enable for Asynchronous DRAM Refresh (ADR) support to enhance memory
performance. The options are Disable and Enable.
Legacy ADR Mode (Available when "Enable fADR" is set to Disable and "Enable
ADR" is set to Enable)
Use this feature to support the Legacy ADR mode to enhance memory performance. In
the Legacy ADR mode, the ADR safe domain (flush domain) includes the WPQ in memory
controllers. The options are Disable, Enable, and Auto.
115
Advertisement
Table of Contents
