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Pin No.
Name
Description
|
69
START
Scan start signal
70
CLK2
Scan clock
71
CLK1/GPIO10 | Key board key control signal
73
LEDCTL
LED control signal
74-77
OPOO - 3
Key button / LED strobe 0 - 3
|
79 - 82
OPIO- 3
Key board return 0 - 3
83 - 86
|
D7-D4
System bus data 7 - 4
88 - 91
D3 - DO
System bus data 3 - 0
94
/RD
Read strobe from CPU
95
WR
Write strobe from CPU
96 - 100
A15
System bus address 15 - 11
|
4,29,78
+5V
17,19,39,53,72,87
GND
3) IFC-P Timing Block Diagram
T=Ims, WATCH DOG
5]
9
(9)
N=(PhasePeriod) + 1
Phase interrupts
1.25ms Motor stepping
8KHz
S
F
EX
; [8 |
yp
Scan line sta
| +8 |
10ms
Print data start
Value indicates
Print strobe start
Current Phase
StbClk | PrtStbOn
T=2ms
2ms interrupt
—=r
Keyboard scan/debounce
LED Control
TSTCLK
(CPUCLK)
6.000035MHz
J
PrtStbPeriod
O=[PriDotPeriod}+1
(14)
G=[StbCikScale]=1
PCLK
PrtBytes
PrtOffset
yw AccDataPos
Cik2Pos, Cik2Neg
3MHz
>
StartPos, StartNeg
ADCSamplePos
VCOPos, VCONeg
Qz=[ScanDotScaler]+1
R=[ScanDotPeriod]+1
(1)
(8)
VC1Pos, VCINeg
ScanBytes
CLK1(150KHz)
[Fig. 4]
4) Scanner Part
@ Scanner Interface
Scanner interface circuit is signal interface with CIS or CCD opto-electrical devices.
This circuit adopts dedicated CIS interface circuit.
CLK 2
: Signal for output to SI lead of image data stored in shift register of CIS by way of CLK 2.
* Dotperiod = (ScanDotScalerperiod) *« (ScanDotPeriod+1)
* ScanDotScalerPeriod = (CPUCLK period) * (ScanDotScaler+- 1)
* ScanDotPeriod and ScanDotScaler is programmable from 0 to 15
START _ : Signal to shift the stored charge from led source to shift register. For the following period the signal is stored.
VIDCTL 0: Digital contro! lead for external signal processing or test circuitry.
VIDCTL 1 : Acts the same as VIDCTL 0.
Used as lead for determining peak detection to realize ABC(auto back - ground control) in the main board.
ADCLK _ : Unused, but originally intended for external 6 bit flash A/D converter A/D clock.
31
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