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IC
MSM82C55A-2GS
MSM82C55A-2GS-VK (OKI)FLAT PACKAGE
C-MOS PROGRAMMABLE PERIPHERAL INTERFACE
— TOP VIEW —
44 43 42 41 40 39 38 37 36 35 34
NC
CS
1
2
GND
A1
3
A0
4
PC7
5
PC6
6
PC5
7
PC4
8
PC0
9
PC1
10
PC2
11
V
DD
NC
(+3 V to +6 V)
12 13 14 15 16 17 18 19 20 21 22
A1
A0
CS
WR
RD
0
0
0
1
0
PORT A
0
1
0
1
0
PORT B
1
0
0
1
0
PORT C
1
1
0
1
0
0
0
0
0
1
DATA BUS
0
1
0
0
1
DATA BUS
1
0
0
0
1
DATA BUS
1
1
0
0
1
DATA BUS
X
X
1
X
X
0
;
LOW LEVEL
A0, A1
CS
1
;
HIGH LEVEL
D0 to 7
;
DON'T CARE
X
PA0 to 7
PB0 to 7
PC0 to 7
RD
WR
DATA
BUS
D0 to D7
BUFFER
RD
WR
RESET
READ/
CS
WRITE
A0
CONTROL
A1
LOGIC
SN74HC00APW-E05
SN74HC00APW-E20 (TI)FLAT PACKAGE
C-MOS QUAD 2-INPUT NAND GATES
-TOP VIEW-
14
13
12
11
10
9
V
DD
1
2
3
4
5
6
NOTE:
TYPE
V
DD
+2 to +5.5V
74AC/74VHC
+4.5 to +5.5V
74ACT/74HCT/74VHCT
LCX
+2 to +3.6V
OTHER TYPES
+2 to +6V
4-8
32
D0
PA0
31
D1
PA1
30
D2
PA2
29
33
RESET
D3
PA3
28
D4
PA4
32
D0
27
D5
PA5
26
31
D1
D6
PA6
25
D7
PA7
30
D2
29
D3
PB0
PB1
28
D4
4
A0
PB2
3
27
D5
A1
PB3
PB4
26
D6
PB5
25
D7
PB6
V
PB7
DD
24
(+3 V to +6 V)
23
PB7
PC0
NC
PC1
PC2
44
RD
PC3
34
WR
PC4
PC5
OPERATION
PC6
1
DATA BUS
CS
PC7
DATA BUS
RESET
DATA BUS
33
NO OPERATION
PORT A
PORT B
PORT C
CONTROL REGISTER
HIGH IMPEDANCE
; PORT SELECT ADDRESS
; CHIP SELECT
; DATA BUS
; PORT A IN/OUT
; PORT B IN/OUT
; PORT C IN/OUT
; READ
; WRITE
GROUP
A
PORT A
GROUP
A
CONTROL
GROUP
A
PORT C
HIGHER
4-BITS
GROUP
B
PORT C
LOWER
GROUP
4-BITS
B
CONTROL
GROUP
B
PORT B
8
A
A
Y =
Y
B
B
Y = A • B = A + B
A
B
Y
0
0
1
GND
0
1
1
7
1
0
1
0 ; LOW LEVEL
1
1
0
1 ; HIGH LEVEL
SN74HC02APW-E05 (TI)
C-MOS QUAD 2-INPUT NOR GATES
-TOP VIEW-
14
13
12
11
V
DD
43
42
41
40
38
37
36
1
2
3
4
35
NOTE:
14
TYPE
15
+2 to +6V
74HC
16
+2 to +5.5V
74AC/74VHC
18
74HCT/74ACT
+4.5 to +5.5V
19
74LCX
+2 to +3.6V
20
21
23
9
10
11
13
8
7
SN74HC04APW-E05
6
SN74HC04APW-E20 (TI)FLAT PACKAGE
5
C-MOS HEX INVERTERS
-TOP VIEW-
14
13
12
11
V
DD
1
2
3
4
NOTE:
TYPE
74AC/74VHC/74VHCT
+2 to +5.5V
74ACT/74HCT
+4.5 to +5.5V
PA0 to PA7
74LCX
+2 to +3.6V
OTHER TYPE
+2 to +6V
PC4 to PC7
SN74HC08APW-E05 (TI)FLAT PACKAGE
PC0 to PC3
C-MOS QUAD 2-INPUT AND GATE
- TOP VIEW -
14
13
12
11
V
DD
PB0 to PB7
1
2
3
4
NOTE :
TYPE
V
AC
+2 to +5.5V
TC40H
+2 to +8V
ACT/HCT
+5V
OTHER TYPES
+2 to +6V
10
9
8
A
Y
= Y
B
Y = A + B = A • B
A
B
Y
0
0
1
GND
0
1
0
5
6
7
1
0
0
1
1
0
0 ; LOW LEVEL
V
DD
1 ; HIGH LEVEL
10
9
8
A
Y =
A
Y = A
A
Y
0
1
1
0
GND
0 ; LOW LEVEL
5
6
7
1 ; HIGH LEVEL
V
DD
A
10
9
8
A
Y =
B
B
Y = A B = A + B
A
B
Y
0
0
0
GND
0
1
0
5
6
7
1
0
0
0
1
1
1
1
DD
A
B
Y
Y
; LOW LEVEL
; HIGH LEVEL
RCP-730
RCP-731
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