Advertisement
XL-MXG9BK:
SLVL
EFMX
rem NT
cryiaA
1-6(No. 20436)
This terminal is aineced to »COM.
It is a request signal | which demands to «COM inputting
the data transfer (YM7121 to zCOM).
This ig a data input terminal connected to .COM. When R/W is high, the data is transferred
from »COM to YM7121
according to the SCK clock input.
These terminals output the PWM to control the speed of spindle motor. The speed of the motor
goes up when DM + is high, and slows down when DM - is high: both terminals can not
become high simultaneously.
When tracks are being crossed during serches, the amplitude variation of the generated HF signal | ls.
samoled at the zero — cross point of the tracking error signal TER and the TROF signal is output. The
level'variations of this signal turn the servo on and off, greatly facilitaing track acquisition. KP + or
- KP ~ is output to conduct tracking, and TRHD is output during tracking to cause generation of the
tracking error signal. The TRGL signal is for increasing the tracking gain after tracking i is completed.
The FEM+
and FEM- are output as high speed feed signals, and FEOF signal is output for
eutang, the feed servo during high speer:| feed.
TRBK is input to apply tracking, brake from outside. TRGL becomes low with high input and
Soe
inner control signal TBKE becomes high.
:
these terminals are used tor controlling the focus servo.
The FCS is for a leading signal of Focusing ; the signal, generated shia the
focus point is achieved, terminate the focusing operation; and FCO flag is Crores unite fray 'by
FRF signal generated when reflected light is detected.
;
YM7121
needs initializing when power supply turn on.
_tC will be low more than 400zs since XIN is input clock with VDD standard.
Amplitude limited, mutually anti-phased signals are output from EFMX and EFMX.
Slice level is controlled by these signals and external amplifier. SLVL is output amplitude
:
alteration component of both terminals. When integral circuit is connected to external, YM7121.
|
easily can control slice level.
- This terminal is input EFM signal.(1~ 2 Vpp)
This terminal outputs the phase difference when the polarity of the ciock and the. EFM pattern
_ changes.
_ This terminal is input DC. velage matched: VCO free run eee
(17. 2872 MHz)
This terminal outputs a half of VPLL input, and capacity for stabilizing is added to this terminal.
Advertisement
