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SE-MXG9BK
Description of ICs
WM MN171X02JHK (1C301) : System controller
1. Terminal Layout
2. Key matrix
;
osct
||
KEYINO
KEY IN1
KEY IN2
2
osc2
i
Pye
dCCT SER
5
x1
:
:
| v2 | SeAONOF | DEMO | __ SOOTHING
d
:
["y3__ [FRONT DAP ON/OFF] _PROLOGIC | _ RELAXING
9
A
DSP ON/OFF
3Ch LOGIC
EXCITING
Loap
FREQUENCY
SQUEEZE
SEA
|
ee
Pye
|
WAC
CLEVE
VOC. MASK
SEA
v7
[ome
evens
[kev cra
MUTE
DOLBYIDAP
SCRATCH
DCS.OUT
FLANGER
DCS.IN
INR.
REMOCON
oniarr
3. Decoder output of 1C302
oe
| [Vi
|v |%[%|% | |
| |
SST
paraaseriny | tf H |e [TH Pt Patt PR] te |
=p
Poatasevem |e fe{H{H|t{t[H]alele |
DSP.DATA
DSP.BUSY
Poaracesrm {i]t {ete fu{[xl{alw[e{-]
DSP.RST
YO~Y9 are the outputs of the shift register 1C302.
| KEY In2
H: power on
rower supply
| 44 | onore |
ras
a6
$1~$17
REMOCON
5 | Remote control signal input
Power supply for FL display'
| INH =| 4 Inhibit signal input
Segment control
47 48 |DCS.IN/OUT VO] Compulink signal
ie
[9 |
=
0 |
[| Pass the DsP circuit, | 49. [DOLBY/DAP
ee
| 50_|
0 |
[0 |
w
N
H
DSP.RST
Reset signal for DSP z-com
SEA.CLK
Clock signal for data transmission to 1C251
DSPREQ [O | Request signal for DSP wcom | 52 | SEADATA
DSP.CLOCK 0 | penal data transmission to | 53 | SCLK
O. Clock for FL driver
37 [psp ausy [0] Data forsen
|
54 | 10A0 [6] Uwich dock output of FL display data
| 38 | DSP.DATA
oO | DSP data signal output
1 ss { yo
jo] FL grid output
;
| 39 | SPICSB
0 | Chip select signal to 1C251
s6~so]
A~D
[0] Grid control/Key matrix output
Strobe signal for data
PISTB
1
NB
.
| «0 | sess Jo transmission to I1€251
|
:
icici
SPEDIN. | | | SPI data from IC251
| 61 | xz
| —| Non connection
Faz_[ seipout [o| control data for casi__| 62 | vss_|-[ono
SSCS
as [reset [1 | Reset signet] ea6a] sca || Onclaton terminal
— nN
Q i
= |
9
%
3
=x
yw
=
1-2 (No.20435)
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