Series Clb Features; Device Resources - Xilinx 7 Series User Manual

Chapter 1: Overview
Approximately two-thirds of the slices are SLICEL logic slices and the rest are SLICEM,
which can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32)
or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic,
arithmetic, and memory features. Expert designers can also instantiate them.

7 Series CLB Features

The 7 series CLB is identical to that in the Virtex®-6 FPGA family. The CLB is very similar
to that of the Spartan®-6 FPGA family with these differences:
•
•
The common features in the CLB structure simplify design migration from the Spartan-6
and Virtex-6 families to the 7 series devices. The unique floorplan means that location
constraints should be removed before implementing designs originally targeted to earlier
FPGAs. The interconnect routing resources are increased in size, quantity, and flexibility
relative to the Virtex-6 FPGA family, improving the quality of automatic place and route
results.

Device Resources

The CLB resources are scalable across all the 7 series families, providing a common
architecture that improves efficiency, IP implementation, and design migration. The
number of CLBs and the ratio between CLBs and other device resources differentiates the
7 series families. Migration between the 7 series families does not require any design
changes for the CLBs.
Device capacity is often measured in terms of logic cells, which are the logical equivalent of
a classic four-input LUT and a flip-flop. The 7 series FPGA CLB six-input LUT, abundant
flip-flops and latches, carry logic, and the ability to create distributed RAM or shift
registers in the SLICEM, increase the effective capacity. The ratio between the number of
logic cells and 6-input LUTs is 1.6:1.
7 Series FPGA CLB Resources
Table 1-1
Kintex®-7, and Virtex®-7 FPGAs. Refer to DS180, 7 Series FPGAs Overview for the most
up-to-date information.
Table 1-1: Spartan-7 FPGA CLB Resources
(1)
Device Slices
(2)
7S6 938
7S15 2,000
10
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Columnar architecture
• Scales easily to higher densities
• More routing between CLBs
SLICEL and SLICEM only (no Spartan-6 FPGA SLICEX)
• All slices support carry logic
• More optimized
through Table 1-4 show the available CLB resources for the Spartan®-7, Artix®-7,
SLICEL SLICEM
658 280
1,400 600
www.xilinx.com
6-input Distributed RAM
LUTs (Kb)
3,752 70
8,000 150
7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
Shift
Register Flip-Flops
(Kb)
35 7,504
75 16,000