Series Fpgas Clocking Differences From Previous Fpga Generations; Key Differences From Virtex-6 Fpgas - Xilinx 7 Series User Manual

Die Level Bank Numbering Overview section in UG475, 7 Series FPGA Packaging and Pinout
Specification.
Region
region variations.
7 Series FPGAs Clocking Differences from Previous FPGA
Generations
The 7 series FPGAs clocking has a similar structure to Virtex-6 FPGAs and supports many
of the same features. However, there are some architectural differences and modifications
to the various clocking elements and their functionality. When compared with
Spartan-6 FPGAs, there are some significant changes in both architecture and functionality.
Some Spartan-6 FPGA clock primitives are no longer available and are replaced by more
powerful and simpler structures.

Key Differences from Virtex-6 FPGAs

•
•
•
•
•
•
•
•
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012

7 Series FPGAs Clocking Differences from Previous FPGA Generations

Appendix B, Clocking Resources and Connectivity Variations per Clock
has detailed figures showing clocking resources and connectivity for the clock
The 7 series FPGAs basic BUFIO clocking functions have not changed with the
exception that the BUFIO now only spans a single bank. Direct clocking of adjacent
banks is replaced by a new clock buffer. There are now four BUFIOs per bank. Similar
to the BUFIO evolution, the basic purpose of the BUFR has not changed. However,
now the BUFR only directly spans a single clock region. There are now four BUFRs
and four regional clocks (tracks) per region.
The 7 series FPGAs introduced a new buffer type: BUFMR/BUFMRCE. The BUFMR/
BUFMRCEs drive BUFIOs and/or BUFRs in the same and vertically adjacent regions.
They also provide the same multi-clock region/multi-bank clock routing available in
Virtex-6 FPGAs which support the same three clock regions/banks capability.
BUFMRCE has a selectable synchronous or asynchronous switching feature.
The global clock (GC) input pins in the Virtex-6 family are no longer supported by the
7 series FPGAs. Four clock-capable clock input pin/pairs per bank replace the GCs.
The connectivity of the clock-capable input pins has been enhanced to support much
of the previous GC capabilities.
The global clock multiplexer BUFGMUX has added an attribute, CLK_SEL_TYPE, for
allowing either synchronous or asynchronous clock switching of the two input clocks
(previously only available through the IGNORE port).
The BUFHCE has an enhanced clock enable to allow for either a synchronous or
asynchronous enable of the input clock.
The CMT now contains one MMCM and one PLL (a subset of the MMCM) instead of
two MMCMs and dedicated memory interface logic which is reserved for Xilinx use
at this time. The CMT column is located adjacent to the SelectIO columns/banks
within the CMT and have dedicated access to the I/Os for high performance. The
global clock buffers are still located in the vertical center of the device between I/O
columns driven by the CMTs. Direct cascading within the CMT is no longer
supported. Cascading to adjacent CMTs directly is possible but limited due to limited
resources. Cascading to other CMTs beyond the adjacent CMTs results in a phase
offset between the source and destination MMCMs/PLLs and requires a special
attribute setting.
Fractional dividers no longer share output counters. This frees up those counters for
other uses. Fractional counters have added a static phase-shift capability.
The CLOCK_HOLD feature is no longer available.
www.xilinx.com 19