Preface: About This Guide; Guide Contents - Xilinx 7 Series User Manual

About This Guide
Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power
to enable a common design to scale across families for optimal power, performance, and
cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the
7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and
bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex®-7 family is
an innovative class of FPGAs optimized for the best price-performance. The Virtex®-7
family is optimized for highest system performance and capacity. This guide serves as a
technical reference describing the 7 series FPGAs configurable logic blocks (CLBs).
Usually, logic synthesis assigns the CLB resources without system designer intervention. It
can be advantageous for the designer to understand certain CLB details, including the
varying capabilities of the look-up tables (LUTs), the physical direction of the carry
propagation, the number and distribution of the available flip-flops, and the availability of
the very efficient shift registers. This guide describes these and other features of the CLB in
detail.
This 7 Series FPGAs Configurable Logic Block User Guide, part of an overall set of
documentation on the 7 series FPGAs, is available on the xilinx.com/documentation.

Guide Contents

This manual contains these chapters:
•
•
•
•
7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
Chapter 1, Overview, provides basic information needed for the majority of users,
including:
• CLB Overview is targeted at the new user.
• 7 Series CLB Features
Virtex®-6 FPGA families for the experienced user and provides design migration
considerations.
• Device Resources indicates the number of resources per device, and unity
between different 7 series families.
• Recommended Design Flow
key aspects to consider.
• Pinout Planning discusses aspects of CLBs that might affect pin placement for a
design.
Chapter 2, Functional Details, lists architectural specifics for each CLB feature.
Chapter 3, Design Entry, provides design entry guidelines and primitives for
instantiation.
Chapter 4, Applications, provides examples that use the CLB resources in larger
applications.
www.xilinx.com
discusses what is new compared with the Spartan®-6 and
provides the basics of using CLB resources and lists
Preface
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