Revision History - Xilinx 7 Series User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
03/01/2011 1.0
03/28/2011 1.1
09/30/2011 1.2
01/30/2012 1.3
11/05/2012 1.4
7 Series FPGAs CLB User Guide
Xilinx Initial release.
Added devices XC7K355T, XC7K420T, and XC7K480T to
have been revised for clarity.
Added last sentence under
Updated CLB features in Table
added ASMBL Architecture
under Carry Logic. Added lasts sentence under
sentence under Slice Multiplexer Timing
Table 5-5 for clarity. Added
section.
Revised Table 1-2. Added fifth paragraph under
Only). Clarified last paragraph under
Changed "uniformity" to "optimized" in last bullet under
Changed "unified" to "scalable" in first sentence under
7A350T device from Table
Added reference to 7 Series FPGA Libraries Guide to
SLICEM Only), Shift Registers (Available in SLICEM
Changed "T " to "T
CEO CECK
Characteristics.
www.xilinx.com
Revision
7 Series CLB Features. Added
1-3. Added first sentence under
section, and CLB Slices heading. Added last paragraph
Using Carry
Parameters. Modified
Devices Using Stacked Silicon Interconnect (SSI) Technology
Distributed RAM (Available in SLICEM
Global Controls GSR and
1-2. Deleted 7V1500T and 7VH290T devices from
" in Figure 5-2 and first bullet under
Table 1-3. Portions of the text
Table 1-3 and Table 1-4.
CLB Arrangement,
Logic. Added second
Table 5-2, Table 5-4, and
GTS.
7 Series CLB Features.
Device Resources. Deleted
Table
Distributed RAM (Available in
Only), and Flip-Flop Primitives.
General Timing
UG474 (v1.8) September 27, 2016
1-4.