Chapter 1: Overview; Clb Overview - Xilinx 7 Series User Manual

Overview

CLB Overview

The 7 series configurable logic block (CLB) provides advanced, high-performance FPGA
logic:
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CLBs are the main logic resources for implementing sequential as well as combinatorial
circuits. Each CLB element is connected to a switch matrix for access to the general routing
matrix (shown in
X-Ref Target - Figure 1-1
The LUTs in 7 series FPGAs can be configured as either a 6-input LUT with one output, or
as two 5-input LUTs with separate outputs but common addresses or logic inputs. Each
5-input LUT output can optionally be registered in a flip-flop. Four such 6-input LUTs and
their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two
slices form a CLB. Four flip-flops per slice (one per LUT) can optionally be configured as
latches. In that case, the remaining four flip-flops in that slice must remain unused.
7 Series FPGAs CLB User Guide
UG474 (v1.8) September 27, 2016
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-input LUT) option
Distributed Memory and Shift Register Logic capability
Dedicated high-speed carry logic for arithmetic functions
Wide multiplexers for efficient utilization
Figure 1-1). A CLB element contains a pair of slices.
Switch
Matrix
Figure 1-1: Arrangement of Slices within the CLB
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COUT COUT
CLB
Slice(1)
Slice(0)
CIN CIN
UG474_c1_01_071910
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