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Intel® Server System SR2612UR TPS
Diagnostic LED Decoder
Checkpoint
Upper Nibble
MSB
8h
4h
2h
LED
#7
#6
#5
Multi-use code (This POST Code is used in different contexts)
0xF2h
O
O
O
Memory Error Codes (Accompanied by a beep code)
0xE8h
O
O
O
0xEAh
O
O
O
0xEBh
O
O
O
0xEDh
O
O
O
0xEEh
O
O
O
Memory Reference Code Progress Codes (Not accompanied by a beep code)
0xB0h
O
X
O
0xB1h
O
X
O
0xB2h
O
X
O
0xB3h
O
X
O
0xB4h
O
X
O
0xB6h
O
X
O
0xB8h
O
X
O
0xB9h
O
X
O
0xBAh
O
X
O
0xBBh
O
X
O
0xBFh
O
X
O
Host Processor
0x04h
X
X
X
0x10h
X
X
X
0x11h
X
X
X
0x12h
X
X
X
0x13h
X
X
X
Chipset
0x21h
X
X
O
Me m o ry
0x22h
X
X
O
0x23h
X
X
O
0x24h
X
X
O
0x25h
X
X
O
0x26h
X
X
O
0x27h
X
X
O
0x28h
X
X
O
PCI Bus
0x50h
X
O
X
0x51h
X
O
X
0x52h
X
O
X
0x53h
X
O
X
0x54h
X
O
X
0x55h
X
O
X
0x56h
X
O
X
Revision 1.3
Table 34. Diagnostic LED POST Code Decoder
O = On, X=Off
Lower Nibble
LSB
1h
8h
4h
2h
1h
#4
#3
#2
#1
#0
O
X
X
O
X
X
O
X
X
X
X
O
X
O
X
X
O
X
O
O
X
O
O
X
O
X
O
O
O
X
O
X
X
X
X
O
X
X
X
O
O
X
X
O
X
O
X
X
O
O
O
X
O
X
X
O
X
O
O
X
O
O
X
X
X
O
O
X
X
O
O
O
X
O
X
O
O
X
O
O
O
O
O
O
O
X
X
O
X
X
O
X
X
X
X
O
X
X
X
O
O
X
X
O
X
O
X
X
O
O
X
X
X
X
O
X
X
X
O
X
X
X
X
O
O
X
X
O
X
X
X
X
O
X
O
X
X
O
O
X
X
X
O
O
O
X
O
X
X
X
O
X
X
X
X
O
X
X
X
O
O
X
X
O
X
O
X
X
O
O
O
X
O
X
X
O
X
O
X
O
O
X
O
O
X
Intel order number E76293-003
Appendix B: POST Code Diagnostic LED Decoder
Seen at the start of Memory Reference Code (MRC)
Start of the very early platform initialization code
Very late in POST, it is the signal that the OS has switched to virtual
memory mode
No Usable Memory Error: No memory in the system, or SPD bad so
no memory could be detected
Channel Training Error: DQ/DQS training failed on a channel during
memory channel initialization.
Memory Test Error: memory failed Hardware BIST.
Population Error: RDIMMs and UDIMMs cannot be mixed in the
system
Mismatch Error: more than 2 Quad Ranked DIMMS in a channel.
Chipset Initialization Phase
Reset Phase
DIMM Detection Phase
Clock Initialization Phase
SPD Data Collection Phase
Rank Formation Phase
Channel Training Phase
Memory Test Phase
Memory Map Creation Phase
RAS Initialization Phase
MRC Complete
Early processor initialization where system BSP is selected
Power-on initialization of the host processor (bootstrap processor)
Host processor cache initialization (including AP)
Starting application processor initialization
SMM initialization
Initializing a chipset component
Reading configuration data from memory (SPD on DIMM)
Detecting presence of memory
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
Initializing memory, such as ECC init
Testing memory
Enumerating PCI buses
Allocating resources to PCI buses
Hot Plug PCI controller initialization
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
Reserved for PCI bus
Description
63
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