Table of Contents
Advertisement
Video Output from
Before the RGB digital video signal leaves the main TV chassis (DG Bd.), it is translated
into a lower voltage, scrambled, and becomes a differential output signal in IC4801.
The destination is the light box digital circuit board (receiver, IC6001) where the RGB
signals are unscrambled and returned to 8 bit R,
differential signals transmitted (sync & clock) are not scrambled.
This Low Voltage Differential Signaling (LVDS) process method has these advantages:
Consumes less total power. The power consumption of a constant current
source is independent of frequency unlike TTL.
Low signal jitter and little generated noise (with constant current output).
Long distance signal transmissions with little amplitude / frequency lo
Mbps capacity for a 1-meter distance or 90 Mbps for a 10-meter run].
Short duration signal losses are acceptable because the scra
process permits signal reconstruction.
TV Assembly (DG Bd.
Inverted R, G, or B signal = 3Vp-p
R, G, B signal at test point = 3Vp-p
LVDS Interface IC
IC4801
L1/pins
2, 5, 8.
= inverted
L1/pins
3, 6, 9.
Figure 41 - LVDS signal
G, & B voltages. The 4
DLP Light Engine (L Bd.)
IC6001
100 ohm test points at L1
Sync signal at test point = 3Vp-p
L1/pin
14 = invert
L1/pins
11 = norm
12 = invert
75.75MHz
Clock signal
44
th
and 5th
ss. [110
mbled (interleaved)
at test point = 3Vp-p
Advertisement
Table of Contents
