3 SPECIFICATIONS
3.4 Buffer Memory
3.4.1 Buffer memory assignment (Q62DAN/Q62DA)
Table 3.7 Buffer memory assignment (Q62DAN/Q62DA) (1/2)
Address
Hexadecimal
Decimal
0
0
H
1
1
H
2
2
H
3
3
H
to
to
A
10
H
B
11
H
C
12
H
D
13
H
to
to
12
18
H
13
19
H
14
20
H
15
21
H
16
22
H
17
23
H
18
24
H
19
25
H
to
to
9D
157
H
9E
158
H
9F
159
H
A0
160
H
to
to
C7
199
H
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The explanation in Section 3.4.5 and later is based on the 8-channel analog output
(CH1 to CH8) Q68DAVN/Q68DAIN/Q68DAV/Q68DAI.
This section describes the assignment of the Q62DAN/Q62DA buffer memory.
POINT
Do not write data from system area or sequence program to the buffer memory
area where writing is disabled. Doing so may cause malfunction.
D/A conversion enable/disable
Setting range (CH1 to CH4)
Offset/gain setting mode Offset specification
Offset/gain setting mode Gain specification
Offset/gain adjustment value specification
Mode switching setting
1 This is the initial value set after the power is turned on or the programmable controller CPU is reset.
2 Indicates whether reading from and writing to a sequence program are enabled.
R : Reading enabled W : Writing enabled
Description
CH1 Digital value
CH2 Digital value
System area
CH1 Set value code
CH2 Set value code
System area
Error code
System area
System area
System area
MELSEC-Q
1
Default
Read/write
3
R/W
H
0
R/W
0
R/W
—
—
0
R
0
R
—
—
0
R/W
0
R
H
—
—
0
R/W
0
R/W
0
R/W
—
—
0
R/W
0
R/W
—
—
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