Advanced Chipset Features - MSI 848PM User Manual

Advanced Chipset Features

MSI Reminds You...
Change these settings only if you are familiar with the chipset.
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [By SPD] enables the following fields auto-
matically to be determined by BIOS based on the configurations on the SPD. Selecting
[Manual] allows users to configure these fields manually.
CAS Latency Time
The fid controls the CAS latency, which determines the timing delay before RAM
starts a read command after receiving it. Setting options are: [2], [2.5], [3]. [2]
increases system performance while [3] provdes more stable system performance.
Active to Precharge Delay
This setting controls the precharge delay, which determines the timing delay for
DRAM precharge. Settings: [5], [6], [7], [8].
DRAM RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance. Setting options: [2], [3], [4].
DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to be allowed
to precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
Setting options: [2], [3], [4].
BIOS Setup
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