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Chapter 3
Configure DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial
Presence Detect) EEPROM on the DRAM module. Setting to
[Enabled] enables RAS# Precharge, RAS# to CAS# Delay,
Precharge Delay, CAS# Latency and Burst Length automatically
to be determined by BIOS based on the configurations on the
SPD. Selecting [Disabled] allows users to configure these fields
manually.
CAS# Latency
This controls the timing delay (in clock cycles) before SDRAM
starts a read command after receiving it. Settings: [2], [2.5], [3]
(clocks). [2] (clocks) increases the system performance the most
while [3] (clocks) provides the most stable performance.
RAS# Precharge
This item controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed
for the RAS to accumulate its charge before DRAM refresh, re-
fresh may be incomplete and DRAM may fail to retain data. This
item applies only when synchronous DRAM is installed in the
system. Available settings: [4], [3], [2] (clocks).
RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of
the transition from RAS (row address strobe) to CAS (column ad-
dress strobe). The less the clock cycles, the faster the DRAM
performance. Available settings: [4], [3], [2] (clocks).
3-12
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