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Module Description
Block diagram and description
The memory may be configured either in block mode or in continuous mode. In block mode, data
collection initiated by a trigger proceeds until a specified block length is captured. The
measurement is then paused so that the data can be read out. This mode is useful in capturing
single transient events or whenever the output data rate is too high to be read and processed in real
time.
In continuous mode, data collection is initiated by a trigger and continues as long as the SDRAM
memory does not overflow. Data may be read out of the memory while the measurement is in
progress. If the reading of data is sufficiently fast, the SDRAM memory never overflows and the
measurement continues indefinitely. If the SDRAM memory should ever overflow then the
measurement stops and waits for data to be read out, the measurement to be re-armed, and a new
trigger to be initiated. This mode of operation is useful for real-time applications that employ a
high speed signal processor to continuously read and operate on each sample of data. Data can be
read from the SDRAM memory in bursts to accommodate pauses for such things as disk access
times or block mode computations.
The effective trigger time may be offset from the actual trigger event by programming a trigger
timing offset. See the Technical Specifications for the limits of the pre-trigger and post-trigger
offset.
Data Output
You can transfer data from the E1439C or E1439D via the VMEbus. With the E1439D, you can
also transmit data via a fiber optic interface and the Local Bus.
To use the VXI backplane, the E1439 can be programmed so that the output of the memory
controller is sent to the Send Data register. The 12- or 24-bit sample data is zero-padded out to 16
or 32 bits. The register can then be read by any controller compatible with the VME standard.
Maximum data flow is about 2 MB/s.
The local bus allows data transfers over a high speed 8-bit ECL bus to an adjacent module (to the
right) in the VXI mainframe. Multiple adjacent E1439D modules can send data to one signal
processor module. The signal processor must be one that supports the Agilent Technologies ECL
local bus protocol, such as the Agilent E9821. In addition to higher speed (up to 66 MB/s), the
local bus has the advantage that data can be output at the same time that control signals are being
sent over the VXI backplane.
The E1439D's fiber optic interface provides data rates greater than 200 MB/s. It is implemented
as a serial FPDP (front panel data port). The serial FPDP is a high-speed low-latency serial
communication link.
In all three of the data output modes, the samples must be read out sequentially, offset by the
trigger delay.
Fiber Optic Interface
The E1439D's fiber optic interface can transmit filtered or unfiltered data, copy data from its
receiver to its transmitter, or append data to copied data. The interface's receiver port is not a data
receiver—it merely copies data to its transmitter port and detects FPDP control signals (e.g., PIO
bits and flow control signals).
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