Table of Contents
Advertisement
Super X11DSF-E User's Manual
Activate PBF (Available when SpeedStep is set to Enable)
Select Enable to enable Prioritized Base Frequency (PBF) feature support which will
enhance CPU performance. The options are Disable and Enable.
Configure PBF (Available when Activate PBF is set to Enable)
Select Enable to allow the BIOS to configure high priority CPU cores as Prioritized Base
Frequency (PBF) so that software programs do not have to configure the PBF (Prioritized
Base Frequency) settings. The options are Enable and Disable.
EIST PSD Function (Available when SpeedStep is set to Enable)
Use this item to configure the processor's P-State coordination settings. During a P-State,
the voltage and frequency of the processor will be reduced when it is in operation. This
makes the processor more energy efficient, resulting in further energy gains. The options
are HW_ALL, SW_ALL and SW-ANY.
Turbo Mode (Available when SpeedStep is set to Enable)
Select Enable for processor cores to run faster than the frequency specified by the
manufacturer. The options are Disable and Enable.
Hardware PM (Power Management) State Control Available when
"Power Technology" is set to Custom)
Hardware P-States
If this feature is set to Disable, hardware will choose a P-state setting for the system based
on an OS request. If this feature is set to Native Mode, hardware will choose a P-state
setting based on OS guidance. If this feature is set to Native Mode with No Legacy Support,
hardware will choose a P-state setting independently without OS guidance. The options
are Disable, Native Mode, Out of Band Mode, and Native Mode with No Legacy Support.
CPU C State Control
Autonomous Core C-State
Select Enable to support Autonomous Core C-State control which will allow the processor
core to control its C-State setting automatically and independently. The options are Disable
and Enable.
CPU C6 Report (Available when Autonomous Core C-State is set to Disable)
Select Enable to allow the BIOS to report the CPU C6 state (ACPI C3) to the operating
system. During the CPU C6 state, power to all caches is turned off. The options are Auto,
Enable, and Disable.
82
Advertisement
Table of Contents
