Cpu Peripheral Block - Panasonic BB-HCM371A Service Manual

- Do not turn off the camera during the reset operation.
12. BLOCK DIAGRAM
13. CIRCUIT DESCRIPTION
13.1. CPU PERIPHERAL BLOCK
- The IC103 is a system LSI for a network camera containing the CPU
- The power supply voltages are +3.3V (I/O) and +1.8V.
- The CPU is a 32-bit RISC CPU and performs mainly hardware control,
TCP/IP protocol processing and applications such as http and FTP.
- The clock setting is 65.536MHz, which is the four times of 16.384MHz
oscillation in the X101 by PLL.
- There are two types of external bus: the General-purpose bus through
SRAM I/F and the bus for SDRAM only.
- The General bus is connected to a Flash Memory for program storage.
- The capacity of the Flash Memory (IC101) is 32Mbit (2Mx16bit); the
program, the setting information for the network camera and the MAC
address are stored.
- The SDRAM (IC105) is 64Mbit (4Mx16bit) and used for the CPU
processing work, the communication data storage and the sound and
image data storage.
- The RESET IC (IC104) monitors the power supply voltage, detects the
rising edge of +3.3V and generates the Hardware Reset Signal.
- The RESTART SW (SW102) is connected to the RESET IC for manual
reset and the hardware is reset by pressing the SW.
- The IC405 is a RTC (Real Time Clock) and is used for the time setting of
the image transfer. It is backed up at power-off by a lithium battery
(BAT401). The I/F with the CPU has a dedicated controller. (5-line I/F)
- The Encryption block inside the IC103 is an Ipsec communication
encryption engine and is used at the software protocol processing.
Signal Flow
1. When a request from the PC is received through LAN, the CGI
command is analyzed at the CPU and the requested image/sound data
are generated.
2. The JPEG image and sound data accumulated on the SDRAM are
formed in IP packet by the protocol processing.
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