Disabling The Sscg Unit - Fujitsu MB86R02 Jade-D Application Note

Emi optimization using sscg
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11 Disabling the SSCG Unit

It is important to follow an specific scheme to disable the SSCG unit in order to avoid causing a spike
on the clock signal of the effected clock domains. Use the following programming sequence:
(example).
Note that the registers used in the following description are in the CRG (Base Address: FFFE_7000)
and the SSCG (Base Address: FFFE_7080) units!
1. Switch the display clock domains to the non-SSCG modulated clock domain:
CSEL <0xFFFE_7034> = 0x00000000
2. Disable the SSCG:
SSCG_ENABLE <0xFFFE_70A4> = 0x00000000
3. Set the SSCG to Bypass mode:
SSCG_CTRL <0xFFFE_70A0*> = 0x00010111
* FFFE_7080 + 20
4. Set the SSCG to Bypass mode and power down the SSCG:
SSCG_CTRL <0xFFFE_70A0> = 0x80010111
A more detailled flow is described in the Hardware Manual.
Version 1.30
17

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