Mitsubishi Electric MELSEC iQ-R Series User Manual page 26

Own station (control CPU, another CPU in a multiple CPU system)
The following table shows the accessible route to a CPU module of the high speed data communication module-mounted
station.
: Accessible, : No combination
Access route
Control CPU
Another CPU in a multiple CPU system
Another station via single network
■Access from the Ethernet port of a high speed data communication module
The following table shows the accessible route when accessing from an Ethernet port of a high speed data communication
module in the status where an access target CPU module is connected to a network.
For the communication target from the Ethernet port of the high speed data communication module, CPU module (Ethernet
port) or Ethernet module can be specified.
: Accessible
Access route
Ethernet
• High speed data communication module Ethernet port  CPU module
(Ethernet port)
• High speed data communication module Ethernet port  Ethernet module
*1 An Ethernet module-mounted station or built-in Ethernet CPU can be accessed. Access via relay station is not possible.
*2 UDP (MELSOFT Connection) needs to be added to the open setting for a built-in Ethernet port of an access target CPU module.
*3 When accessing an Ethernet port of Q12DCCPU-V (Basic mode) directly, MELSOFT connection needs to be permitted in the
Q12DCCPU-V (Basic mode) setting.
For details on the setting, refer to the following:
 C Controller Module User's Manual (Utility Operation, Programming)
2 SPECIFICATIONS
24
2.2 Access Specifications for a CPU Module
Access target CPU module (series)
RCPU QCPU (Q mode)
Programm C Programm
able Controller able
controller module controller
CPU/ CPU/
Process Process
CPU/ CPU
Safety
CPU
  
  
(CPU No.1 to (CPU No.1 to
No.4) No.4)
Access target CPU module (series)
RCPU QCPU (Q mode)
Programm C Programm
able Controller able
controller module controller
CPU/ CPU/
Process Process
CPU/ CPU
Safety
CPU
  
(CPU No.1 to (CPU No.1 to (CPU No.1 to
No.4) No.4) No.4)
LCPU
C Programm
Controller able
module controller
CPU
 
 
LCPU
C Programm
Controller able
module controller
CPU
*1*2 *3 *2
 
(Host CPU)