Timing For Control Signal; Timing For Analog Output Control Signal - Contec DA16-16L User Manual

6. About Hardware

Timing for Control Signal

Timing for Analog Output Control Signal

Figures 6.3, 6.4, 6.5, and Table 6.3 shows the timing for analog output control signal.
External Smapling Clock Input
Conversion start
Figure 6.3. Timing for External Sampling Clock (Analog output)
External Smapling Start Trigger Input
Figure 6.4. Timing for Sampling Start Control Signal
External Smapling Stop Trigger Input
Figure 6.5. Timing for Sampling Stop Control Signal
Table 6.3. Timing List for Control Signal
Delay from external sampling clock to actual start
Settling time
Set up time of sampling start (Rising edge)
Hold time of sampling start (Rising edge)
Set up time of sampling start (Falling edge)
Hold time of sampling start (Falling edge)
Set up time of sampling stop (Rising edge)
Hold time of sampling stop (Rising edge)
Set up time of sampling stop (Falling edge)
Hold time of sampling stop (Falling edge)
CAUTION
The times listed in Table 6.3 are for standard operating conditions.
68
t
DEC
t t
SRS HRS
t t
SRP HRP
Parameter
t t
SFS HFS
t t
SFP HFP
Symbol Time Unit
t 100 nsec
DEC
t 10000 nsec
WS
t 100 nsec
SRS
t 100 nsec
HRS
t 100 nsec
SFS
t 100 nsec
HFS
t 100 nsec
SRP
t 100 nsec
HRP
t 100 nsec
SFP
t 100 nsec
HFP
DA16-16(LPCI)L, DA16-8(LPCI)L